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authorTim Wawrzynczak <twawrzynczak@chromium.org>2019-04-30 12:52:29 -0600
committerPatrick Georgi <pgeorgi@google.com>2019-05-22 10:09:23 +0000
commitd93531bcc8a216d9bc82a7f13444833943a270d7 (patch)
treef7ac9a2a3548dba92f526daa0f3da1f870264938 /src/soc/intel/cannonlake/Makefile.inc
parentfa6233daeb2bfb8b75bea9032c0839e2d5bcf60d (diff)
downloadcoreboot-d93531bcc8a216d9bc82a7f13444833943a270d7.tar.xz
soc/intel/cannonlake: Dump ME f/w version and status information
At the end of device enable, print the ME f/w version number. Before resume or loading payload, dump the ME's Host Firmware Status registers. BUG=b:131437724 BRANCH=none TEST=Prints seemingly sane values on WHL and CML devices. Change-Id: Ibeb3a2a85cd84c9baa45f90f20a3dcf69f7d5646 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32527 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/cannonlake/Makefile.inc')
-rw-r--r--src/soc/intel/cannonlake/Makefile.inc1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc
index 7ad0c7c82c..13289448b6 100644
--- a/src/soc/intel/cannonlake/Makefile.inc
+++ b/src/soc/intel/cannonlake/Makefile.inc
@@ -43,6 +43,7 @@ ramstage-y += gspi.c
ramstage-y += i2c.c
ramstage-y += lockdown.c
ramstage-y += lpc.c
+ramstage-y += me.c
ramstage-y += memmap.c
ramstage-y += nhlt.c
ramstage-y += p2sb.c