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authorLijian Zhao <lijian.zhao@intel.com>2017-07-11 12:26:56 -0700
committerAaron Durbin <adurbin@chromium.org>2017-08-07 17:53:13 +0000
commite88fa490a5248c0de6d51b07d4ede885f09637b6 (patch)
treeb08ea849c27aa06f34731e90991d0c087d665b1e /src/soc/intel/cannonlake/Makefile.inc
parent8da22868851e752ce7c633551f74ef3ef8bf4b6c (diff)
downloadcoreboot-e88fa490a5248c0de6d51b07d4ede885f09637b6.tar.xz
soc/intel/cannonlake: Add memory map support
Calculate the top of ram from output of Fsp reserved memory range. Change-Id: I0dcc8f737c5811c9010cc4a20ea0126ab3f90f14 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/20533 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/cannonlake/Makefile.inc')
-rw-r--r--src/soc/intel/cannonlake/Makefile.inc3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc
index 480e0477ad..537a973a61 100644
--- a/src/soc/intel/cannonlake/Makefile.inc
+++ b/src/soc/intel/cannonlake/Makefile.inc
@@ -11,8 +11,9 @@ bootblock-y += bootblock/cpu.c
bootblock-y += bootblock/pch.c
bootblock-y += bootblock/report_platform.c
bootblock-y += gpio.c
+bootblock-y += memmap.c
-romstage-y += cbmem.c
+romstage-y += memmap.c
romstage-y += reset.c
romstage-$(CONFIG_DRIVERS_UART_8250MEM) += uart.c