diff options
author | praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com> | 2018-09-27 00:00:13 +0800 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2018-10-17 12:16:47 +0000 |
commit | 521e48c87da6c70644a03c7b5e77856a8e556e53 (patch) | |
tree | 67db1fc9a1a1748f8977756d6138f4489ee7ab4d /src/soc/intel/cannonlake/acpi/gpio_cnp_h.asl | |
parent | e26c4a461132087930e7137043ab6ada1b4147c7 (diff) | |
download | coreboot-521e48c87da6c70644a03c7b5e77856a8e556e53.tar.xz |
soc/intel/cannonlake: Add CNP PCH-H gpio pin definitions
- CNL PCH-H has 12 GPIO groups which are grouped under 5 gpio communities.
- Add gpio pin definitions for CNP-H and related changes.
- Add gpio device name, host software ownership reg offset for CNP-H.
BUG: none
TEST: build and flash, boot to windows and yocto os on both CFL RVP8 &
RVP11 and verify power management, IO device functionalities
work fine.
Change-Id: I496ec059de125b97c646581bbd3b8bfe6ffa641e
Signed-off-by: praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>
Reviewed-on: https://review.coreboot.org/28890
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/cannonlake/acpi/gpio_cnp_h.asl')
-rw-r--r-- | src/soc/intel/cannonlake/acpi/gpio_cnp_h.asl | 128 |
1 files changed, 128 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/acpi/gpio_cnp_h.asl b/src/soc/intel/cannonlake/acpi/gpio_cnp_h.asl new file mode 100644 index 0000000000..6e6eccf361 --- /dev/null +++ b/src/soc/intel/cannonlake/acpi/gpio_cnp_h.asl @@ -0,0 +1,128 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <soc/gpio_defs_cnp_h.h> +#include <soc/irq.h> +#include <soc/pcr_ids.h> + + +Device (GPIO) +{ + Name (_HID, "INT3450") + Name (_UID, 0) + Name (_DDN, "GPIO Controller") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0, COM0) + Memory32Fixed (ReadWrite, 0, 0, COM1) + Memory32Fixed (ReadWrite, 0, 0, COM2) + Memory32Fixed (ReadWrite, 0, 0, COM3) + Memory32Fixed (ReadWrite, 0, 0, COM4) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) + { GPIO_IRQ14 } + }) + + Method (_CRS, 0, NotSerialized) + { + /* GPIO Community 0 */ + CreateDWordField (^RBUF, ^COM0._BAS, BAS0) + CreateDWordField (^RBUF, ^COM0._LEN, LEN0) + Store (^^PCRB (PID_GPIOCOM0), BAS0) + Store (GPIO_BASE_SIZE, LEN0) + + /* GPIO Community 1 */ + CreateDWordField (^RBUF, ^COM1._BAS, BAS1) + CreateDWordField (^RBUF, ^COM1._LEN, LEN1) + Store (^^PCRB (PID_GPIOCOM1), BAS1) + Store (GPIO_BASE_SIZE, LEN1) + + /* GPIO Community 2 */ + CreateDWordField (^RBUF, ^COM2._BAS, BAS2) + CreateDWordField (^RBUF, ^COM2._LEN, LEN2) + Store (^^PCRB (PID_GPIOCOM2), BAS2) + Store (GPIO_BASE_SIZE, LEN2) + + /* GPIO Community 3 */ + CreateDWordField (^RBUF, ^COM3._BAS, BAS3) + CreateDWordField (^RBUF, ^COM3._LEN, LEN3) + Store (^^PCRB (PID_GPIOCOM3), BAS3) + Store (GPIO_BASE_SIZE, LEN3) + + + /* GPIO Community 4 */ + CreateDWordField (^RBUF, ^COM4._BAS, BAS4) + CreateDWordField (^RBUF, ^COM4._LEN, LEN4) + Store (^^PCRB (PID_GPIOCOM4), BAS4) + Store (GPIO_BASE_SIZE, LEN4) + + Return (RBUF) + } + + Method (_STA, 0, NotSerialized) + { + Return (0xF) + } +} + +/* + * Get GPIO DW0 Address + * Arg0 - GPIO Number + */ +Method (GADD, 1, NotSerialized) +{ + /* GPIO Community 0 */ + If (LAnd (LGreaterEqual (Arg0, GPP_A0), LLessEqual (Arg0, GPP_B23))) + { + Store (PID_GPIOCOM0, Local0) + Subtract (Arg0, GPP_A0, Local1) + } + /* GPIO Community 1 */ + If (LAnd (LGreaterEqual (Arg0, GPP_C0), LLessEqual (Arg0, GPP_G7))) + { + Store (PID_GPIOCOM1, Local0) + Subtract (Arg0, GPP_C0, Local1) + } + /* GPIO Community 3*/ + If (LAnd (LGreaterEqual (Arg0, GPP_K0), LLessEqual (Arg0, GPP_F23))) + { + Store (PID_GPIOCOM3, Local0) + Subtract (Arg0, GPP_K0, Local1) + } + /* GPIO Community 4*/ + If (LAnd (LGreaterEqual (Arg0, GPP_I0), LLessEqual (Arg0, GPP_J11))) + { + Store (PID_GPIOCOM4, Local0) + Subtract (Arg0, GPP_I0, Local1) + } + Store (PCRB (Local0), Local2) + Add (Local2, PAD_CFG_BASE, Local2) + Return (Add (Local2, Multiply (Local1, 16))) +} + +/* + * Get GPIO Value + * Arg0 - GPIO Number + */ +Method (GRXS, 1, Serialized) +{ + OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) + Field (PREG, AnyAcc, NoLock, Preserve) + { + VAL0, 32 + } + And (GPIORXSTATE_MASK, ShiftRight (VAL0, GPIORXSTATE_SHIFT), Local0) + + Return (Local0) +} |