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author | Lijian Zhao <lijian.zhao@intel.com> | 2017-10-02 19:18:16 -0700 |
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committer | Aaron Durbin <adurbin@chromium.org> | 2017-10-05 21:16:46 +0000 |
commit | ae565463b6a7ad4edad76ff8e2f52e1176bf8783 (patch) | |
tree | 4e605592b4d55dee959ff9c5a83a27dd10d01819 /src/soc/intel/cannonlake/acpi/smbus.asl | |
parent | d3476809955ffb69447cc02a5ea893ebd1da3eb3 (diff) | |
download | coreboot-ae565463b6a7ad4edad76ff8e2f52e1176bf8783.tar.xz |
soc/intel/cannonlake: Add all the SOC level DSDT tables
Add all the SOC level DSDT tables, reference from skylake/kabylake.
Change-Id: Ia72bbe87b32d37db01f8768bd8447cb6ee1567a9
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21860
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/cannonlake/acpi/smbus.asl')
-rw-r--r-- | src/soc/intel/cannonlake/acpi/smbus.asl | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/acpi/smbus.asl b/src/soc/intel/cannonlake/acpi/smbus.asl new file mode 100644 index 0000000000..cd5ba2c822 --- /dev/null +++ b/src/soc/intel/cannonlake/acpi/smbus.asl @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +// Intel SMBus Controller 0:1f.4 + +Device (SBUS) +{ + Name (_ADR, 0x001f0004) +} |