diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2019-10-30 13:32:36 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-01 11:49:48 +0000 |
| commit | 1e8f305957c98cb224574e1fa81938c9a692bd48 (patch) | |
| tree | 4e8673f3aad87958355af2fdecbb613214d6395e /src/soc/intel/cannonlake/acpi/southbridge.asl | |
| parent | 96ca0d93d2309c796eb0d3075fe094a5f500c530 (diff) | |
| download | coreboot-1e8f305957c98cb224574e1fa81938c9a692bd48.tar.xz | |
soc/intel/{apl,cnl,dnv,icl,skl}: Move lpc.asl into common/block/acpi
This patch creates a common instance of lpc.asl inside intel common
code (soc/intel/common/block/acpi/acpi) and asks specific soc code to
refer lpc.asl from common code block.
Note: From ICL onwards Intel Bus Device 0:1f.0 is known as eSPI
rather than LPC.
TEST=Able to build and boot ICL DE system. Dump DSDT.asl to verify
Device(LPCB) device presence after booting to OS.
Change-Id: I266d6e667e7ae794377e4882791e3be933d35e87
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36455
Reviewed-by: Michael Niewöhner
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/cannonlake/acpi/southbridge.asl')
| -rw-r--r-- | src/soc/intel/cannonlake/acpi/southbridge.asl | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/cannonlake/acpi/southbridge.asl b/src/soc/intel/cannonlake/acpi/southbridge.asl index 8ba3d89b0f..b52de65e36 100644 --- a/src/soc/intel/cannonlake/acpi/southbridge.asl +++ b/src/soc/intel/cannonlake/acpi/southbridge.asl @@ -32,7 +32,7 @@ #endif /* LPC 0:1f.0 */ -#include "lpc.asl" +#include <soc/intel/common/block/acpi/acpi/lpc.asl> /* PCH HDA */ #include "pch_hda.asl" |