diff options
| author | praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com> | 2018-09-27 00:00:13 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-10-17 12:16:47 +0000 |
| commit | 521e48c87da6c70644a03c7b5e77856a8e556e53 (patch) | |
| tree | 67db1fc9a1a1748f8977756d6138f4489ee7ab4d /src/soc/intel/cannonlake/acpi/southbridge.asl | |
| parent | e26c4a461132087930e7137043ab6ada1b4147c7 (diff) | |
| download | coreboot-521e48c87da6c70644a03c7b5e77856a8e556e53.tar.xz | |
soc/intel/cannonlake: Add CNP PCH-H gpio pin definitions
- CNL PCH-H has 12 GPIO groups which are grouped under 5 gpio communities.
- Add gpio pin definitions for CNP-H and related changes.
- Add gpio device name, host software ownership reg offset for CNP-H.
BUG: none
TEST: build and flash, boot to windows and yocto os on both CFL RVP8 &
RVP11 and verify power management, IO device functionalities
work fine.
Change-Id: I496ec059de125b97c646581bbd3b8bfe6ffa641e
Signed-off-by: praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>
Reviewed-on: https://review.coreboot.org/28890
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/cannonlake/acpi/southbridge.asl')
| -rw-r--r-- | src/soc/intel/cannonlake/acpi/southbridge.asl | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/acpi/southbridge.asl b/src/soc/intel/cannonlake/acpi/southbridge.asl index ff323c40a3..49b5f6e509 100644 --- a/src/soc/intel/cannonlake/acpi/southbridge.asl +++ b/src/soc/intel/cannonlake/acpi/southbridge.asl @@ -33,7 +33,11 @@ #include "scs.asl" /* GPIO controller */ +#if IS_ENABLED(CONFIG_SOC_INTEL_CANNONLAKE_PCH_H) +#include "gpio_cnp_h.asl" +#else #include "gpio.asl" +#endif /* LPC 0:1f.0 */ #include "lpc.asl" |