diff options
| author | Bora Guvendik <bora.guvendik@intel.com> | 2017-09-13 18:39:16 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-09-19 23:19:53 +0000 |
| commit | 67fb347668eb9aa85936daf140af72c4384cf5f5 (patch) | |
| tree | 75aba31613b80177d1d032a4db871182134009f3 /src/soc/intel/cannonlake/acpi/southbridge.asl | |
| parent | a0e0b054bd086d09d0577c6c1548acae45bb3176 (diff) | |
| download | coreboot-67fb347668eb9aa85936daf140af72c4384cf5f5.tar.xz | |
soc/intel/cannonlake: Add PCIE IRQs
Change-Id: Iea99baaa58d2212e7d09a19aaac9d303226f7c5e
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/21530
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/cannonlake/acpi/southbridge.asl')
| -rw-r--r-- | src/soc/intel/cannonlake/acpi/southbridge.asl | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/acpi/southbridge.asl b/src/soc/intel/cannonlake/acpi/southbridge.asl new file mode 100644 index 0000000000..3d6538e200 --- /dev/null +++ b/src/soc/intel/cannonlake/acpi/southbridge.asl @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corp. + * (Written by Bora Guvendik <bora.guvendik@intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/* PCI IRQ assignment */ +#include "pci_irqs.asl" |