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| author | Subrata Banik <subrata.banik@intel.com> | 2018-09-30 01:39:49 +0530 |
|---|---|---|
| committer | Duncan Laurie <dlaurie@chromium.org> | 2018-10-09 20:12:01 +0000 |
| commit | a0729899d7aa2764b83ba7b8c00fe36a4bb3fb2e (patch) | |
| tree | fe53266c8e39afcd8a2db30006f31020a973a890 /src/soc/intel/cannonlake/acpi/southbridge.asl | |
| parent | 50cdce95751d25e73abfe0bdd02c95029db8b7df (diff) | |
| download | coreboot-a0729899d7aa2764b83ba7b8c00fe36a4bb3fb2e.tar.xz | |
soc/intel/cannonlake: Make correct IRQ mapping for CNL SA and PCH PCI devices
This patch provides option for PCI IRQ mapping in both PIC and APIC mode.
TEST=Build and Boot on CNL RVP.
Change-Id: Ie26750ac9dc2ce940b0c116085c041de439075df
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/28799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/cannonlake/acpi/southbridge.asl')
| -rw-r--r-- | src/soc/intel/cannonlake/acpi/southbridge.asl | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/acpi/southbridge.asl b/src/soc/intel/cannonlake/acpi/southbridge.asl index 6fac398619..2b34df5037 100644 --- a/src/soc/intel/cannonlake/acpi/southbridge.asl +++ b/src/soc/intel/cannonlake/acpi/southbridge.asl @@ -15,6 +15,13 @@ * GNU General Public License for more details. */ +#include <intelblocks/itss.h> +#include <intelblocks/pcr.h> +#include <soc/itss.h> +#include <soc/pcr_ids.h> + +/* Interrupt Routing */ +#include "irqlinks.asl" /* PCI IRQ assignment */ #include "pci_irqs.asl" |