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| author | Subrata Banik <subrata.banik@intel.com> | 2018-09-30 01:41:45 +0530 |
|---|---|---|
| committer | Duncan Laurie <dlaurie@chromium.org> | 2018-10-09 20:12:17 +0000 |
| commit | c8a842b708e0affe95dc87ae80912987d7f4682a (patch) | |
| tree | 73984d47345586dcbe6fabb1c8062172def5b9e9 /src/soc/intel/cannonlake/acpi/southbridge.asl | |
| parent | a0729899d7aa2764b83ba7b8c00fe36a4bb3fb2e (diff) | |
| download | coreboot-c8a842b708e0affe95dc87ae80912987d7f4682a.tar.xz | |
soc/intel/cannonlake: Add PCIE ASL entry
This patch creates _PRT entires for each PCIE root port devices.
TEST=Able to see PCIE wake device in cat /proc/acpi/wake list
Change-Id: I183c89c92139e15e0bfc39620710dbdc6597b351
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/28800
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/cannonlake/acpi/southbridge.asl')
| -rw-r--r-- | src/soc/intel/cannonlake/acpi/southbridge.asl | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/acpi/southbridge.asl b/src/soc/intel/cannonlake/acpi/southbridge.asl index 2b34df5037..ff323c40a3 100644 --- a/src/soc/intel/cannonlake/acpi/southbridge.asl +++ b/src/soc/intel/cannonlake/acpi/southbridge.asl @@ -41,6 +41,9 @@ /* PCH HDA */ #include "pch_hda.asl" +/* PCIE Ports */ +#include "pcie.asl" + /* Serial IO */ #include "serialio.asl" |