soc/intel/{apl,cnl,dnv,icl,skl}: Move lpc.asl into common/block/acpi

This patch creates a common instance of lpc.asl inside intel common
code (soc/intel/common/block/acpi/acpi) and asks specific soc code to
refer lpc.asl from common code block.

Note: From ICL onwards Intel Bus Device 0:1f.0 is known as eSPI
rather than LPC.

TEST=Able to build and boot ICL DE system. Dump DSDT.asl to verify
Device(LPCB) device presence after booting to OS.

Change-Id: I266d6e667e7ae794377e4882791e3be933d35e87
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36455
Reviewed-by: Michael Niewöhner
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

2 files changed, 1 insertions, 118 deletions

diff --git a/src/soc/intel/cannonlake/acpi/lpc.asl b/src/soc/intel/cannonlake/acpi/lpc.asl
deleted file mode 100644
index f1c1bf3bc3..0000000000
--- a/src/soc/intel/cannonlake/acpi/lpc.asl
+++ /dev/null
@@ -1,117 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-Device (LPCB)
-{
-	Name (_ADR, 0x001f0000)
-	Name (_DDN, "LPC Bus Device")
-
-	Device (FWH)
-	{
-		Name (_HID, EISAID ("INT0800"))
-		Name (_DDN, "Firmware Hub")
-		Name (_CRS, ResourceTemplate ()
-		{
-			Memory32Fixed (ReadOnly, 0xff000000, 0x01000000)
-		})
-	}
-
-	Device (HPET)
-	{
-		Name (_HID, EISAID ("PNP0103"))
-		Name (_DDN, "High Precision Event Timer")
-		Name (_CRS, ResourceTemplate ()
-		{
-			Memory32Fixed (ReadWrite, HPET_BASE_ADDRESS, 0x400)
-		})
-		Method (_STA, 0)
-		{
-			Return (0xf)
-		}
-	}
-
-	Device (PIC)
-	{
-		Name (_HID, EISAID ("PNP0000"))
-		Name (_DDN, "8259 Interrupt Controller")
-		Name (_CRS, ResourceTemplate()
-		{
-			IO (Decode16, 0x20, 0x20, 0x01, 0x02)
-			IO (Decode16, 0x24, 0x24, 0x01, 0x02)
-			IO (Decode16, 0x28, 0x28, 0x01, 0x02)
-			IO (Decode16, 0x2c, 0x2c, 0x01, 0x02)
-			IO (Decode16, 0x30, 0x30, 0x01, 0x02)
-			IO (Decode16, 0x34, 0x34, 0x01, 0x02)
-			IO (Decode16, 0x38, 0x38, 0x01, 0x02)
-			IO (Decode16, 0x3c, 0x3c, 0x01, 0x02)
-			IO (Decode16, 0xa0, 0xa0, 0x01, 0x02)
-			IO (Decode16, 0xa4, 0xa4, 0x01, 0x02)
-			IO (Decode16, 0xa8, 0xa8, 0x01, 0x02)
-			IO (Decode16, 0xac, 0xac, 0x01, 0x02)
-			IO (Decode16, 0xb0, 0xb0, 0x01, 0x02)
-			IO (Decode16, 0xb4, 0xb4, 0x01, 0x02)
-			IO (Decode16, 0xb8, 0xb8, 0x01, 0x02)
-			IO (Decode16, 0xbc, 0xbc, 0x01, 0x02)
-			IO (Decode16, 0x4d0, 0x4d0, 0x01, 0x02)
-			IRQNoFlags () { 2 }
-		})
-	}
-
-	Device (LDRC)
-	{
-		Name (_HID, EISAID ("PNP0C02"))
-		Name (_UID, 2)
-		Name (_DDN, "Legacy Device Resources")
-		Name (_CRS, ResourceTemplate ()
-		{
-			IO (Decode16, 0x2e, 0x2e, 0x1, 0x02) // First SuperIO
-			IO (Decode16, 0x4e, 0x4e, 0x1, 0x02) // Second SuperIO
-			IO (Decode16, 0x61, 0x61, 0x1, 0x01) // NMI Status
-			IO (Decode16, 0x63, 0x63, 0x1, 0x01) // CPU Reserved
-			IO (Decode16, 0x65, 0x65, 0x1, 0x01) // CPU Reserved
-			IO (Decode16, 0x67, 0x67, 0x1, 0x01) // CPU Reserved
-			IO (Decode16, 0x80, 0x80, 0x1, 0x01) // Port 80 Post
-			IO (Decode16, 0x92, 0x92, 0x1, 0x01) // CPU Reserved
-			IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI
-			IO (Decode16, ACPI_BASE_ADDRESS, ACPI_BASE_ADDRESS,
-			    0x1, 0xff)
-		})
-	}
-
-	Device (RTC)
-	{
-		Name (_HID, EISAID ("PNP0B00"))
-		Name (_DDN, "Real Time Clock")
-		Name (_CRS, ResourceTemplate ()
-		{
-			IO (Decode16, 0x70, 0x70, 1, 8)
-		})
-	}
-
-	Device (TIMR)
-	{
-		Name (_HID, EISAID ("PNP0100"))
-		Name (_DDN, "8254 Timer")
-		Name (_CRS, ResourceTemplate ()
-		{
-			IO (Decode16, 0x40, 0x40, 0x01, 0x04)
-			IO (Decode16, 0x50, 0x50, 0x10, 0x04)
-			IRQNoFlags () {0}
-		})
-	}
-
-}
diff --git a/src/soc/intel/cannonlake/acpi/southbridge.asl b/src/soc/intel/cannonlake/acpi/southbridge.asl
index 8ba3d89b0f..b52de65e36 100644
--- a/src/soc/intel/cannonlake/acpi/southbridge.asl
+++ b/src/soc/intel/cannonlake/acpi/southbridge.asl
@@ -32,7 +32,7 @@
 #endif
 
 /* LPC 0:1f.0 */
-#include "lpc.asl"
+#include <soc/intel/common/block/acpi/acpi/lpc.asl>
 
 /* PCH HDA */
 #include "pch_hda.asl"