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| author | praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com> | 2018-09-20 03:49:45 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-10-17 12:16:21 +0000 |
| commit | e26c4a461132087930e7137043ab6ada1b4147c7 (patch) | |
| tree | 14ed0f62eb89c5197d0d783991947ac9e5207083 /src/soc/intel/cannonlake/chip.c | |
| parent | da5491a626955480ae07f5cb944d8aff66a172d0 (diff) | |
| download | coreboot-e26c4a461132087930e7137043ab6ada1b4147c7.tar.xz | |
soc/intel/cannonlake: Add new cannon lake PCH-H support
Cannon lake PCH-H is added to support coffee lake RVP11 and coffee lake
RVP8 platforms.
- Add new device IDs for LPC, PCIE, PMC, I2C, UART, SMBUS, XHCI, P2SB,
SRAM, AUDIO, CSE0, XDCI, SD, MCH and graphics device.
- Add new device IDs to intel common code respectively.
- Add CPU, LPC, GD, MCH entry to report_platform.c to identify RVP11 & RVP8.
- CNL PCH-H supports 24 pcie root ports and 4 I2C controllers, hence chip.c
is modified accordingly.
- Add board type UserBd UPD to BOARD_TYPE_DESKTOP for both RVP11 & RVP8.
BUG=None
TEST=successfully boot both CFL RVP11 & RVP8, verified all the enabled devices
are enumerated and cross checked devices ids in serial logs and UEFI shell.
Change-Id: I4b6af88d467382250aecb4102878b1c5af92ccd4
Signed-off-by: praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>
Reviewed-on: https://review.coreboot.org/28718
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/cannonlake/chip.c')
| -rw-r--r-- | src/soc/intel/cannonlake/chip.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c index 0529c5ca8c..4049c1e78c 100644 --- a/src/soc/intel/cannonlake/chip.c +++ b/src/soc/intel/cannonlake/chip.c @@ -75,6 +75,14 @@ const char *soc_acpi_name(const struct device *dev) case PCH_DEVFN_PCIE14: return "RP14"; case PCH_DEVFN_PCIE15: return "RP15"; case PCH_DEVFN_PCIE16: return "RP16"; + case PCH_DEVFN_PCIE17: return "RP17"; + case PCH_DEVFN_PCIE18: return "RP18"; + case PCH_DEVFN_PCIE19: return "RP19"; + case PCH_DEVFN_PCIE20: return "RP20"; + case PCH_DEVFN_PCIE21: return "RP21"; + case PCH_DEVFN_PCIE22: return "RP22"; + case PCH_DEVFN_PCIE23: return "RP23"; + case PCH_DEVFN_PCIE24: return "RP24"; case PCH_DEVFN_UART0: return "UAR0"; case PCH_DEVFN_UART1: return "UAR1"; case PCH_DEVFN_GSPI0: return "SPI0"; |