summaryrefslogtreecommitdiff
path: root/src/soc/intel/cannonlake/chip.c
diff options
context:
space:
mode:
authorLijian Zhao <lijian.zhao@intel.com>2017-09-05 18:16:21 -0700
committerAaron Durbin <adurbin@chromium.org>2017-09-13 22:56:09 +0000
commit08231833232d9cf80072e77c3f039a303bd6ffbb (patch)
tree9d46556c5b489ad8d5730b6a47356f51f25fa927 /src/soc/intel/cannonlake/chip.c
parent1210026bda8ad1fa24d2f0a7625f5b2cd35662ed (diff)
downloadcoreboot-08231833232d9cf80072e77c3f039a303bd6ffbb.tar.xz
soc/intel/cannonlake: Add serialio device config
Add SerialIO device mode configuration, device mode definition mirrored from FSP. Change-Id: I7009120d69646cf60cb5a622e438ae1eeb6498cf Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21411 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/cannonlake/chip.c')
-rw-r--r--src/soc/intel/cannonlake/chip.c40
1 files changed, 40 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c
index ab546337e4..42a59ceec4 100644
--- a/src/soc/intel/cannonlake/chip.c
+++ b/src/soc/intel/cannonlake/chip.c
@@ -86,6 +86,43 @@ static const char *soc_acpi_name(struct device *dev)
}
#endif
+static void parse_devicetree(FSP_S_CONFIG *params)
+{
+ struct device *dev = SA_DEV_ROOT;
+ if (!dev) {
+ printk(BIOS_ERR, "Could not find root device\n");
+ return;
+ }
+
+ const config_t *config = dev->chip_info;
+ const int SerialIoDev[] = {
+ PCH_DEVFN_I2C0,
+ PCH_DEVFN_I2C1,
+ PCH_DEVFN_I2C2,
+ PCH_DEVFN_I2C3,
+ PCH_DEVFN_I2C4,
+ PCH_DEVFN_I2C5,
+ PCH_DEVFN_GSPI0,
+ PCH_DEVFN_GSPI1,
+ PCH_DEVFN_GSPI2,
+ PCH_DEVFN_UART0,
+ PCH_DEVFN_UART1,
+ PCH_DEVFN_UART2
+ };
+
+ for (int i = 0; i < ARRAY_SIZE(SerialIoDev); i++) {
+ dev = dev_find_slot(0, SerialIoDev[i]);
+ if (!dev->enabled) {
+ params->SerialIoDevMode[i] = PchSerialIoDisabled;
+ continue;
+ }
+ params->SerialIoDevMode[i] = PchSerialIoPci;
+ if (config->SerialIoDevMode[i] == PchSerialIoAcpi ||
+ config->SerialIoDevMode[i] == PchSerialIoHidden)
+ params->SerialIoDevMode[i] = config->SerialIoDevMode[i];
+ }
+}
+
void soc_init_pre_device(void *chip_info)
{
/* Perform silicon specific init. */
@@ -137,6 +174,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
const struct device *dev = SA_DEV_ROOT;
const config_t *config = dev->chip_info;
+ /* Parse device tree and enable/disable devices */
+ parse_devicetree(params);
+
/* Set USB OC pin to 0 first */
for (i = 0; i < ARRAY_SIZE(params->Usb2OverCurrentPin); i++) {
params->Usb2OverCurrentPin[i] = 0;