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| author | Lijian Zhao <lijian.zhao@intel.com> | 2017-08-17 14:25:24 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-09-13 03:09:15 +0000 |
| commit | 2b074d90ae0d20f2d3171f2ddc5d0b6c0d3b78b0 (patch) | |
| tree | 1d06a3e7633e227a071e60bf6325ae345cc12e6c /src/soc/intel/cannonlake/chip.h | |
| parent | 6732b4fcdcb48b21631ca73cd1ec37f497d21d3e (diff) | |
| download | coreboot-2b074d90ae0d20f2d3171f2ddc5d0b6c0d3b78b0.tar.xz | |
soc/intel/cannonlake: Add common ACPI support for CNL
Basic ACPI support for CNL on top of common ACPI, which will establish
a root of FADT table, fill MADT entry, create gnvs field, record wake
status and convert device names into DSDT dev definitions.
Change-Id: Ibc16d2afdd3cb9bad2ecb85cf320c88504409707
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21076
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/cannonlake/chip.h')
| -rw-r--r-- | src/soc/intel/cannonlake/chip.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 0ed41fc824..52a5fc13a3 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -108,6 +108,11 @@ struct soc_intel_cannonlake_config { struct usb3_port_config usb3_ports[10]; uint8_t XdciEnable; uint8_t SsicPortEnable; + /* Wake Enable Bitmap for USB2 ports */ + uint16_t usb2_wake_enable_bitmap; + /* Wake Enable Bitmap for USB3 ports */ + uint16_t usb3_wake_enable_bitmap; + /* SATA related */ uint8_t SataEnable; @@ -194,6 +199,7 @@ struct soc_intel_cannonlake_config { * 0x02000000 - 32MiB and beyond */ uint32_t PrmrrSize; + uint8_t PmTimerDisabled; }; typedef struct soc_intel_cannonlake_config config_t; |