soc/intel/cnl: replace the remains of HeciEnabled by device state in dt

The option `HeciEnabled` was partly replaced by use of the device on/off
state in the devicetree in commit 3de90d1. The option has been removed
from the corresponding boards, so `HeciEnabled` is always 0 and ME
always gets disabled during soc finalize, when `HECI_DISABLE_USING_SMM`
is set.

Replace the option in the finalize function by the same dt state check
that sets the FSP option and drop the remaints of `HeciEnabled`.

Devicetrees still having `HeciEnabled` have been adapted to keep the
current behaviour.

Change-Id: Ib4cca9099b9aa3434552a41fbafca7cf6a0dd0eb
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47195
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 0 insertions, 3 deletions

diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index 2a52627be7..a084f67b46 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -253,9 +253,6 @@ struct soc_intel_cannonlake_config {
 	 * 0 = System Agent, 1 = IA Core, 2 = Ring,
 	 * 3 = GT unsliced,  4 = GT sliced */
 	struct vr_config domain_vr_config[NUM_VR_DOMAINS];
-	/* HeciEnabled decides the state of Heci1 at end of boot
-	 * Setting to 0 (default) disables Heci1 and hides the device from OS */
-	uint8_t HeciEnabled;
 
 	/* Enables support for Teton Glacier hybrid storage device */
 	uint8_t TetonGlacierMode;