diff options
| author | Edward O'Callaghan <quasisec@google.com> | 2020-02-21 16:08:04 +1100 |
|---|---|---|
| committer | Edward O'Callaghan <quasisec@chromium.org> | 2020-02-28 03:28:30 +0000 |
| commit | fa043c4e9d8ee07aba02eb9c7bdbe41e4848f5a9 (patch) | |
| tree | 9198da9d5c3006256a53e22be84662851b3f5969 /src/soc/intel/cannonlake/chip.h | |
| parent | d51665600e0ddbd4e1ae7144e29d179287ec285f (diff) | |
| download | coreboot-fa043c4e9d8ee07aba02eb9c7bdbe41e4848f5a9.tar.xz | |
soc/intel/cannonlake: Plumb TetonGlacierMode into dt
The following plumbs through the enabling of Intel's TetonGlacierMode
allows for reconfiguring the PCIe lanes at runtime for hybrid drives
to be accessable via devicetree.
BUG=b:149171631
BRANCH=none
TEST=Swap between x4 NVMe drives and 2x2 Teton Glacier hybrid drives and
run lsblk, lspci, and nvme tools to confirm dynamic PCIe configuration
on Puff.
Change-Id: Id9a72161494db6a4da4abd3302b06df7c70634ab
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38846
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/cannonlake/chip.h')
| -rw-r--r-- | src/soc/intel/cannonlake/chip.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index fd37d26492..752ec1f315 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -242,6 +242,9 @@ struct soc_intel_cannonlake_config { * Setting to 0 (default) disables Heci1 and hides the device from OS */ uint8_t HeciEnabled; + /* Enables support for Teton Glacier hybrid storage device */ + uint8_t TetonGlacierMode; + /* PL1 Override value in Watts */ uint32_t tdp_pl1_override; /* PL2 Override value in Watts */ |