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| author | Aamir Bohra <aamir.bohra@intel.com> | 2019-12-09 16:05:52 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-02-04 16:14:50 +0000 |
| commit | 4d9d3f164de7002dd38f12dc40f9b260f63d2d9b (patch) | |
| tree | f49b32b7c994c45f73174f519791681f8c371927 /src/soc/intel/cannonlake/chip.h | |
| parent | d8663e0fc6629835eba44cc78e63e285aced897f (diff) | |
| download | coreboot-4d9d3f164de7002dd38f12dc40f9b260f63d2d9b.tar.xz | |
soc/intel/cannonlake: Allow Audio DSP OSC qualification for low power idle
With Audio DSP OSC qualification disabled from S0ix criteria.
S0ix is achieved before the DSP is suspended. When driver tries
to suspend DSP its already turned off.
BUG=b:139481313
Change-Id: I20b793b95483af03ce4ae068ac07864a9e90d39b
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37604
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/cannonlake/chip.h')
| -rw-r--r-- | src/soc/intel/cannonlake/chip.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 0712146544..fd37d26492 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -59,8 +59,13 @@ struct soc_intel_cannonlake_config { uint32_t gen3_dec; uint32_t gen4_dec; + /* S0ix configuration */ + /* Enable S0iX support */ int s0ix_enable; + /* Enable Audio DSP oscillator qualification for S0ix */ + uint8_t cppmvric2_adsposcdis; + /* Enable DPTF support */ int dptf_enable; |