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authorKrishna Prasad Bhat <krishna.p.bhat.d@intel.com>2019-03-14 23:23:22 +0530
committerPatrick Georgi <pgeorgi@google.com>2019-03-25 11:03:13 +0000
commit2de19038beffa154eefe40755b607aa9f94d9f9f (patch)
tree46d9927c074aadbc2b58d10e20b3ae29d57f619a /src/soc/intel/cannonlake/finalize.c
parentc53e6ed62f36b8532306815b1258a337650a3d1d (diff)
downloadcoreboot-2de19038beffa154eefe40755b607aa9f94d9f9f.tar.xz
soc/intel/cannonlake: Clear PMCON status bits
The prev_sleep_state value was showing 5 even after warm reboot, once the SUS_PWR_FLR bit is being set. This bit was not being cleared. Hence clearing the PMCON status bits. BUG=b:128482282 BRANCH=None TEST=In cbmem logs, check for value of “prev_sleep_state” using command cbmem –c | grep “prev_sleep_state” For cold reboot, "prev_sleep_state 5" For warm reboot, "prev_sleep_state 0" Change-Id: If9863d52ed3c61b6a160df53f023b0787eaaed68 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31902 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Diffstat (limited to 'src/soc/intel/cannonlake/finalize.c')
-rw-r--r--src/soc/intel/cannonlake/finalize.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/finalize.c b/src/soc/intel/cannonlake/finalize.c
index bc4ae02d66..e334555ac0 100644
--- a/src/soc/intel/cannonlake/finalize.c
+++ b/src/soc/intel/cannonlake/finalize.c
@@ -85,6 +85,8 @@ static void pch_finalize(void)
}
pch_handle_sideband(config);
+
+ pmc_clear_pmcon_sts();
}
static void soc_finalize(void *unused)