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author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-09-28 00:20:27 +0300 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2019-10-02 11:21:10 +0000 |
commit | d5f645c6cde230004ee5af6c62d451d1329928e9 (patch) | |
tree | eb87509c96e5ee1fa26e87594c75a399d92402e2 /src/soc/intel/cannonlake/finalize.c | |
parent | d3d38c95b7c23c5bd455d35e1b5bef0bce7b2cc5 (diff) | |
download | coreboot-d5f645c6cde230004ee5af6c62d451d1329928e9.tar.xz |
soc/intel: Replace config_of_path() with config_of_soc()
The previously provided device path made no difference, all
integrated PCI devices point back to the same chip_info
structure.
Change reduces the exposure of various SA_DEVFN_xx and
PCH_DEVFN_xx from (ugly) soc/pci_devs.h.
Change-Id: Ibf13645fdd3ef7fd3d5c8217bb24d7ede045c790
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35656
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/cannonlake/finalize.c')
-rw-r--r-- | src/soc/intel/cannonlake/finalize.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/cannonlake/finalize.c b/src/soc/intel/cannonlake/finalize.c index c99653b75a..115b73254e 100644 --- a/src/soc/intel/cannonlake/finalize.c +++ b/src/soc/intel/cannonlake/finalize.c @@ -84,7 +84,7 @@ static void pch_finalize(void) * point and hence removed from the root bus. pcidev_path_on_root thus * returns NULL for PCH_DEV_PMC device. */ - config = config_of_path(SA_DEVFN_ROOT); + config = config_of_soc(); pmcbase = pmc_mmio_regs(); if (config->PmTimerDisabled) { reg8 = read8(pmcbase + PCH_PWRM_ACPI_TMR_CTL); |