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| author | Felix Singer <felix.singer@secunet.com> | 2020-08-19 14:13:15 +0200 |
|---|---|---|
| committer | Michael Niewöhner <c0d3z3r0@review.coreboot.org> | 2020-09-04 11:50:30 +0000 |
| commit | d9e459428de519c89b23f9a7465bcb7b835c08a0 (patch) | |
| tree | 956464b00cdcfdc67de63e304ece77fe2b8d249d /src/soc/intel/cannonlake/fsp_params.c | |
| parent | 5127cb8b16654a10cc06942be1574bae86804348 (diff) | |
| download | coreboot-d9e459428de519c89b23f9a7465bcb7b835c08a0.tar.xz | |
soc/intel/cnl: Enable HECI3 depending on devicetree
Currently HECI3 gets enabled by the option Heci3Enabled, but this
duplicates the devicetree on/off options. Therefore depend on the
devicetree for enablement of the HECI3 controller.
All corresponding mainboards were checked if the devicetree
configuration matches the Heci3Enabled setting, and divergent
devicetrees were adjusted.
Change-Id: Ic7d52096aee225c2ced1e1bc29ca850fe5073edc
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44579
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/cannonlake/fsp_params.c')
| -rw-r--r-- | src/soc/intel/cannonlake/fsp_params.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 51ed2a8b57..615a94f32e 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -525,7 +525,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) else params->ScsUfsEnabled = dev->enabled; - params->Heci3Enabled = config->Heci3Enabled; + dev = pcidev_path_on_root(PCH_DEVFN_CSE_3); + params->Heci3Enabled = is_dev_enabled(dev); #if !CONFIG(HECI_DISABLE_USING_SMM) dev = pcidev_path_on_root(PCH_DEVFN_CSE); params->Heci1Disabled = !is_dev_enabled(dev); |