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| author | Marx Wang <marx.wang@intel.com> | 2020-02-07 16:44:14 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-02-25 10:11:02 +0000 |
| commit | 9318d6d6251dcc5ae243a377d15d407a066ec46f (patch) | |
| tree | 4ed813f2fc7dfd0ea9829cb6e297849a0561e7e8 /src/soc/intel/cannonlake/include | |
| parent | 75cd6d2a97a3d5630e74ca099ddb702be143415e (diff) | |
| download | coreboot-9318d6d6251dcc5ae243a377d15d407a066ec46f.tar.xz | |
soc/intel/cannonlake: Add TDC config for CML
Add Thermal Design Current (TDC) defaults for CML:
1. TdcEnable
2. TdcPowerLimit
BUG=b:148912093
BRANCH=None
TEST=build coreboot and Intel FSP with fw_debug enabled, flash image to
the device, capture the log from the serial port during boot-up and
check TdcEnable and TdcPowerLimit for each domain in captured log
Signed-off-by: Marx Wang <marx.wang@intel.com>
Change-Id: Ie4b17e5b4ce41c1adb436ae5646f0d8578a440e8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/intel/cannonlake/include')
| -rw-r--r-- | src/soc/intel/cannonlake/include/soc/vr_config.h | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/include/soc/vr_config.h b/src/soc/intel/cannonlake/include/soc/vr_config.h index 1390b174e1..456db5b48f 100644 --- a/src/soc/intel/cannonlake/include/soc/vr_config.h +++ b/src/soc/intel/cannonlake/include/soc/vr_config.h @@ -53,10 +53,18 @@ struct vr_config { /* AC and DC Loadline in 1/100 mOhms. Range is 0-6249 */ uint16_t ac_loadline; uint16_t dc_loadline; + + /* Thermal Design Current (TDC) Power Limit will take effect when + this is set to 0 */ + uint8_t tdc_disable; + + /* Thermal Design Current (TDC) Power Limit in 1/8 A units */ + uint16_t tdc_powerlimit; }; #define VR_CFG_AMP(i) (uint16_t)((i) * 4) #define VR_CFG_MOHMS(i) (uint16_t)((i) * 100) +#define VR_CFG_TDC_AMP(i) (uint16_t)((i) * 8) /* VrConfig Settings for 4 domains * 0 = System Agent, 1 = IA Core, @@ -85,6 +93,14 @@ enum vr_domain { [VR_GT_SLICED] = VR_CFG_MOHMS(gt_sl), \ } +#define VR_CFG_ALL_DOMAINS_TDC(sa, ia, gt_unsl, gt_sl) \ + { \ + [VR_SYSTEM_AGENT] = VR_CFG_TDC_AMP(sa), \ + [VR_IA_CORE] = VR_CFG_TDC_AMP(ia), \ + [VR_GT_UNSLICED] = VR_CFG_TDC_AMP(gt_unsl), \ + [VR_GT_SLICED] = VR_CFG_TDC_AMP(gt_sl), \ + } + void fill_vr_domain_config(void *params, int domain, const struct vr_config *cfg); |