diff options
| author | Lijian Zhao <lijian.zhao@intel.com> | 2017-10-10 18:26:18 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-10-18 17:52:11 +0000 |
| commit | 6cf501c3ae0278092cb76ccab015ad891af1fd48 (patch) | |
| tree | 4e50e2379607bc2c4a6211a63f15797637fef184 /src/soc/intel/cannonlake/include | |
| parent | 53660ed499fa2a523de4d7619fd1067f64f564fb (diff) | |
| download | coreboot-6cf501c3ae0278092cb76ccab015ad891af1fd48.tar.xz | |
soc/intel/cannonlake: Add finalize function
Before OS boot up, the following actions need to be taken.
1. Lock down PMC/SPI/DMI/TCO register.
2. Disable Sideband Access.
3. Disable Heci interface.
4. Disable PMtimer base on config settings.
TEST=Boot up into OS properly on both cannonlake y and cannonlake u rvp
board.
Change-Id: Icfa05b50fd76fbaeb856d398918990aedac4c5e6
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21943
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/cannonlake/include')
| -rw-r--r-- | src/soc/intel/cannonlake/include/soc/pmc.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/include/soc/pmc.h b/src/soc/intel/cannonlake/include/soc/pmc.h index a98b4bad7f..fd28859fa3 100644 --- a/src/soc/intel/cannonlake/include/soc/pmc.h +++ b/src/soc/intel/cannonlake/include/soc/pmc.h @@ -120,6 +120,9 @@ #define GBLRST_CAUSE0_THERMTRIP (1 << 5) #define GBLRST_CAUSE1 0x1928 +#define CPPMVRIC 0x1B1C +#define XTALSDQDIS (1 << 22) + #define IRQ_REG ACTL #define SCI_IRQ_ADJUST 0 #define ACTL 0x1BD8 |