diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2018-05-17 18:40:32 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-01-10 12:18:34 +0000 |
| commit | 7bc4dc5648c6ff37a847e99d7acee11e3e72a79d (patch) | |
| tree | c7137be28a68c96d3711c77ef7bbd9d288d6569f /src/soc/intel/cannonlake/include | |
| parent | e7184b0ad07b0d3fe3e2f58bacd5e10e3cd88a79 (diff) | |
| download | coreboot-7bc4dc5648c6ff37a847e99d7acee11e3e72a79d.tar.xz | |
soc/intel/common/block: Move tco common functions into block/smbus
This patch cleans soc/intel/{apl/cnl/icl/skl} by moving common soc
code into common/block/smbus.
BUG=b:78109109
BRANCH=NONE
TEST=Build and boot KBL/CNL/APL/ICL platform.
Change-Id: I34b33922cafee9f31702587e0f9c03b64f0781b8
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/26166
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/soc/intel/cannonlake/include')
| -rw-r--r-- | src/soc/intel/cannonlake/include/soc/smbus.h | 13 |
1 files changed, 4 insertions, 9 deletions
diff --git a/src/soc/intel/cannonlake/include/soc/smbus.h b/src/soc/intel/cannonlake/include/soc/smbus.h index 9f1cf34862..e3d93a2a54 100644 --- a/src/soc/intel/cannonlake/include/soc/smbus.h +++ b/src/soc/intel/cannonlake/include/soc/smbus.h @@ -4,7 +4,7 @@ * Copyright (C) 2005 Yinghai Lu <yinghailu@gmail.com> * Copyright (C) 2009 coresystems GmbH * Copyright (C) 2014 Google Inc. - * Copyright (C) 2017 Intel Corporation. + * Copyright (C) 2017-2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -19,11 +19,6 @@ #ifndef _SOC_CANNONLAKE_SMBUS_H_ #define _SOC_CANNONLAKE_SMBUS_H_ -/* PCI registers */ -#define TCOBASE 0x50 /* TCO base address. */ -#define TCOCTL 0x54 -#define TCO_BASE_EN (1 << 8) /* TCO base enable. */ - /* IO and MMIO registers under primary BAR */ /* Set address for PCH as SMBus slave role */ #define SMB_RCV_SLVA 0x09 @@ -32,10 +27,10 @@ #define TCO1_STS 0x04 #define TCO_TIMEOUT (1 << 3) #define TCO2_STS 0x06 -#define TCO2_STS_SECOND_TO (1 << 1) +#define TCO_STS_SECOND_TO (1 << 1) #define TCO1_CNT 0x08 -#define TCO_LOCK (1 << 12) -#define TCO_TMR_HLT (1 << 11) +#define TCO_LOCK (1 << 12) +#define TCO_TMR_HLT (1 << 11) /* * Default slave address value for PCH. This value is set to match default |