diff options
author | Lijian Zhao <lijian.zhao@intel.com> | 2017-09-05 18:16:21 -0700 |
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committer | Aaron Durbin <adurbin@chromium.org> | 2017-09-13 22:56:09 +0000 |
commit | 08231833232d9cf80072e77c3f039a303bd6ffbb (patch) | |
tree | 9d46556c5b489ad8d5730b6a47356f51f25fa927 /src/soc/intel/cannonlake/include | |
parent | 1210026bda8ad1fa24d2f0a7625f5b2cd35662ed (diff) | |
download | coreboot-08231833232d9cf80072e77c3f039a303bd6ffbb.tar.xz |
soc/intel/cannonlake: Add serialio device config
Add SerialIO device mode configuration, device mode definition mirrored
from FSP.
Change-Id: I7009120d69646cf60cb5a622e438ae1eeb6498cf
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21411
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/cannonlake/include')
-rw-r--r-- | src/soc/intel/cannonlake/include/soc/serialio.h | 43 |
1 files changed, 43 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/include/soc/serialio.h b/src/soc/intel/cannonlake/include/soc/serialio.h new file mode 100644 index 0000000000..e152770024 --- /dev/null +++ b/src/soc/intel/cannonlake/include/soc/serialio.h @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SERIALIO_H_ +#define _SERIALIO_H_ + +typedef enum { + PchSerialIoDisabled, + PchSerialIoPci, + PchSerialIoAcpi, + PchSerialIoHidden, +} PCH_SERIAL_IO_MODE; + +typedef enum { + PchSerialIoIndexI2C0, + PchSerialIoIndexI2C1, + PchSerialIoIndexI2C2, + PchSerialIoIndexI2C3, + PchSerialIoIndexI2C4, + PchSerialIoIndexI2C5, + PchSerialIoIndexSPI0, + PchSerialIoIndexSPI1, + PchSerialIoIndexSPI2, + PchSerialIoIndexUART0, + PchSerialIoIndexUART1, + PchSerialIoIndexUART2, + PchSerialIoIndexMAX +} PCH_SERIAL_IO_CONTROLLER; + +#endif |