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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2019-03-21 15:38:06 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2019-04-26 16:49:13 +0000 |
| commit | c3385070d6e86dbde71dddbdef94ffa5579f9d11 (patch) | |
| tree | e2d65c2c0550b67092d008ca31c3c22e11b932f0 /src/soc/intel/cannonlake/include | |
| parent | 9df72e0471296d9bc2981646490c1f8b5b1e54e0 (diff) | |
| download | coreboot-c3385070d6e86dbde71dddbdef94ffa5579f9d11.tar.xz | |
soc/{amd,intel}/chip: Use local include for chip.h
Change-Id: Ic1fcbf4b54b7d0b5cda04ca9f7fc145050c867b8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32014
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/soc/intel/cannonlake/include')
| -rw-r--r-- | src/soc/intel/cannonlake/include/soc/ramstage.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/soc/intel/cannonlake/include/soc/ramstage.h b/src/soc/intel/cannonlake/include/soc/ramstage.h index 4a96185e6b..486839852c 100644 --- a/src/soc/intel/cannonlake/include/soc/ramstage.h +++ b/src/soc/intel/cannonlake/include/soc/ramstage.h @@ -17,11 +17,12 @@ #ifndef _SOC_RAMSTAGE_H_ #define _SOC_RAMSTAGE_H_ -#include <chip.h> #include <device/device.h> #include <fsp/api.h> #include <fsp/util.h> +#include "../../chip.h" + void mainboard_silicon_init_params(FSP_S_CONFIG *params); void soc_init_pre_device(void *chip_info); |