summaryrefslogtreecommitdiff
path: root/src/soc/intel/cannonlake/include
diff options
context:
space:
mode:
authorLijian Zhao <lijian.zhao@intel.com>2019-03-13 10:52:49 -0700
committerDuncan Laurie <dlaurie@chromium.org>2019-03-29 14:55:54 +0000
commit009e6cbf842ae1e28231d8e864403c68857c337a (patch)
treef44780887e102d7eca5d2015b866aa4eb13984b3 /src/soc/intel/cannonlake/include
parent06d0705834efc74281ccad7b8958b0e24dc2c701 (diff)
downloadcoreboot-009e6cbf842ae1e28231d8e864403c68857c337a.tar.xz
soc/intel/cannonlake: Ignore GBE LTR
Ignore integrated GBE controller LTR setting to make it wake up from s0ix with 10/100M cable attached. BUG=b:122435844 TEST= Test on sarien platorm, after the changes sytem can wake by WOL, and also checked SLP_S0 residency can increase with 10/100M cable and battery connected. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: Iec7dd197b8a456751f8e4dcb19e3e153f5888613 Reviewed-on: https://review.coreboot.org/c/coreboot/+/31888 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Diffstat (limited to 'src/soc/intel/cannonlake/include')
-rw-r--r--src/soc/intel/cannonlake/include/soc/pmc.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/include/soc/pmc.h b/src/soc/intel/cannonlake/include/soc/pmc.h
index 95cca65ab2..67854d4cbd 100644
--- a/src/soc/intel/cannonlake/include/soc/pmc.h
+++ b/src/soc/intel/cannonlake/include/soc/pmc.h
@@ -145,6 +145,9 @@
#define GBLRST_CAUSE0_THERMTRIP (1 << 5)
#define GBLRST_CAUSE1 0x1928
+#define LTR_IGN 0x1B0C
+#define IGN_GBE (1 << 3)
+
#define CPPMVRIC 0x1B1C
#define XTALSDQDIS (1 << 22)