diff options
| author | Lijian Zhao <lijian.zhao@intel.com> | 2017-07-07 12:25:20 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-07-19 23:06:07 +0000 |
| commit | 0ade3133a0565df7b917a0f82869b10c3d4c57d4 (patch) | |
| tree | 4bf7a062009ba9bff96c97d4003124c8582f977c /src/soc/intel/cannonlake/include | |
| parent | e8253fea6308afd186bb349b8f5b831f7d2c9381 (diff) | |
| download | coreboot-0ade3133a0565df7b917a0f82869b10c3d4c57d4.tar.xz | |
soc/intel/cannonlake: Add minimal changes to call FSP Memoryinit
The following minimal changes are needed to make system boot until FSP
memoryinit got called.
1. Program SA BARs
2. Assume previous power state is S0.
Change-Id: Iab96b27d4220acf4089b901bca28018eaba940a1
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20497
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/cannonlake/include')
| -rw-r--r-- | src/soc/intel/cannonlake/include/soc/pm.h | 28 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/include/soc/romstage.h | 26 |
2 files changed, 49 insertions, 5 deletions
diff --git a/src/soc/intel/cannonlake/include/soc/pm.h b/src/soc/intel/cannonlake/include/soc/pm.h index 9c7c41a91e..d69250776c 100644 --- a/src/soc/intel/cannonlake/include/soc/pm.h +++ b/src/soc/intel/cannonlake/include/soc/pm.h @@ -1,7 +1,8 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corporation. + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015-2016 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -13,9 +14,26 @@ * GNU General Public License for more details. */ -#ifndef _SOC_CANNONLAKE_PM_H_ -#define _SOC_CANNONLAKE_PM_H_ +#ifndef _SOC_PM_H_ +#define _SOC_PM_H_ -/* nothing here yet. Thanks for looking, though! */ +#include <arch/acpi.h> +#include <soc/pmc.h> -#endif
\ No newline at end of file +struct chipset_power_state { + uint16_t pm1_sts; + uint16_t pm1_en; + uint32_t pm1_cnt; + uint16_t tco1_sts; + uint16_t tco2_sts; + uint32_t gpe0_sts[4]; + uint32_t gpe0_en[4]; + uint32_t gen_pmcon_a; + uint32_t gen_pmcon_b; + uint32_t gblrst_cause[2]; + uint32_t prev_sleep_state; +} __attribute__ ((packed)); + +struct chipset_power_state *fill_power_state(void); + +#endif diff --git a/src/soc/intel/cannonlake/include/soc/romstage.h b/src/soc/intel/cannonlake/include/soc/romstage.h new file mode 100644 index 0000000000..2cdbaa57c1 --- /dev/null +++ b/src/soc/intel/cannonlake/include/soc/romstage.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015-2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_ROMSTAGE_H_ +#define _SOC_ROMSTAGE_H_ + +#include <arch/cpu.h> +#include <fsp/api.h> + +void mainboard_memory_init_params(FSPM_UPD *mupd); +void systemagent_early_init(void); + +#endif /* _SOC_ROMSTAGE_H_ */ |