diff options
| author | Duncan Laurie <dlaurie@google.com> | 2019-01-23 14:58:23 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-01-25 11:22:22 +0000 |
| commit | 26bc3282f6ed8f4cc54b06df180fa47d3e646cab (patch) | |
| tree | 65fd6c6c2db8c08fb32f62d503fdc3e370bc00bd /src/soc/intel/cannonlake/include | |
| parent | 52b5b587f1bc5d23d20959f1cae664038d6a42ea (diff) | |
| download | coreboot-26bc3282f6ed8f4cc54b06df180fa47d3e646cab.tar.xz | |
soc/intel/cannonlake: Export function to set After G3 state
Export the SOC level function to set the After G3 state so it
can be changed by the mainboard. The setting will be restored
by a normal boot but in some circumstances coreboot wants to
ensure that it will be powered up again after a reset.
BUG=b:121380403
TEST=update cr50 firmware on sarien and reboot and ensure the
host does not power off after the cr50 initiated reset.
Change-Id: I6cd572ac91229584b9907f87bb4b340963203c32
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31056
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/cannonlake/include')
| -rw-r--r-- | src/soc/intel/cannonlake/include/soc/pmc.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/include/soc/pmc.h b/src/soc/intel/cannonlake/include/soc/pmc.h index 992e60deac..c3957d39c8 100644 --- a/src/soc/intel/cannonlake/include/soc/pmc.h +++ b/src/soc/intel/cannonlake/include/soc/pmc.h @@ -162,4 +162,8 @@ #define SCIS_IRQ21 5 #define SCIS_IRQ22 6 #define SCIS_IRQ23 7 + +struct device; +void pmc_set_afterg3(struct device *dev, int s5pwr); + #endif |