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| author | Jeremy Soller <jeremy@system76.com> | 2019-02-20 16:39:55 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-17 08:24:09 +0000 |
| commit | 1af482c9c9679cb7a6b54dfd74c88eb4c9ee8de5 (patch) | |
| tree | 4ebd3ec0afb22366b9523ff65710b0af9e7eb51a /src/soc/intel/cannonlake/lpc.c | |
| parent | b6e2afb1ffe7683118ba879ca19ef6343f641d17 (diff) | |
| download | coreboot-1af482c9c9679cb7a6b54dfd74c88eb4c9ee8de5.tar.xz | |
soc/intel/cannonlake: Set correct serirq mode
Set FSP params PchSirqEnable/PchSirqMode based on board
setting of serirq_mode. Matches implementation on Skylake.
This is a no-change for existing boards since the default
remains SERIRQ_QUIET mode.
Tested on system76 galp3-c, out-of-tree WHL-U board
Change-Id: I9ad4f5a6c7391fc6e813ec1306c708f449a69f59
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31536
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Nathaniel L Desimone <nathaniel.l.desimone@intel.com>
Diffstat (limited to 'src/soc/intel/cannonlake/lpc.c')
| -rw-r--r-- | src/soc/intel/cannonlake/lpc.c | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/src/soc/intel/cannonlake/lpc.c b/src/soc/intel/cannonlake/lpc.c index c4eb884a75..8b9802220e 100644 --- a/src/soc/intel/cannonlake/lpc.c +++ b/src/soc/intel/cannonlake/lpc.c @@ -210,6 +210,8 @@ static void pch_misc_init(void) void lpc_soc_init(struct device *dev) { + const config_t *config = dev->chip_info; + /* Legacy initialization */ isa_dma_init(); pch_misc_init(); @@ -218,10 +220,7 @@ void lpc_soc_init(struct device *dev) lpc_enable_pci_clk_cntl(); /* Set LPC Serial IRQ mode */ - if (CONFIG(SERIRQ_CONTINUOUS_MODE)) - lpc_set_serirq_mode(SERIRQ_CONTINUOUS); - else - lpc_set_serirq_mode(SERIRQ_QUIET); + lpc_set_serirq_mode(config->serirq_mode); /* Interrupt configuration */ pch_enable_ioapic(dev); |