diff options
| author | Maulik V Vaghela <maulik.v.vaghela@intel.com> | 2018-07-17 21:52:27 +0530 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-08-30 14:47:04 +0000 |
| commit | 9b08a189667b74c220b5359755dc88cdfc08c950 (patch) | |
| tree | d76543b2a7173aa4d4506581a03f0006537ef2fa /src/soc/intel/cannonlake/lpc.c | |
| parent | 58344fc2e7d9256524997b5aecd6130534c6702c (diff) | |
| download | coreboot-9b08a189667b74c220b5359755dc88cdfc08c950.tar.xz | |
soc/intel/cannonlake: Update PMC base address for CNP H and LP
PMC base address is different for CNP LP pch and CNP H pch.
Added logic to determine PMC base addrress dynamically based on PCH ID.
BUG=none
BRANCH=none
TEST=Boot Coffeelake U RVP board and check if PMC base address is
determined correctly.
Change-Id: I833395260e8fb631823bd03192a092df323250fa
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/27523
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/cannonlake/lpc.c')
| -rw-r--r-- | src/soc/intel/cannonlake/lpc.c | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/lpc.c b/src/soc/intel/cannonlake/lpc.c index d399d1bcaf..84a2138efd 100644 --- a/src/soc/intel/cannonlake/lpc.c +++ b/src/soc/intel/cannonlake/lpc.c @@ -68,6 +68,24 @@ void soc_setup_dmi_pcr_io_dec(uint32_t *gen_io_dec) pcr_write32(PID_DMI, PCR_DMI_LPCLGIR4, gen_io_dec[3]); } +uint8_t get_pch_series(void) +{ + uint16_t lpc_did_hi_byte; + + /* + * Fetch upper 8 bits on LPC device ID to determine PCH type + * Adding 1 to the offset to fetch upper 8 bits + */ + lpc_did_hi_byte = pci_read_config8(PCH_DEV_LPC, PCI_DEVICE_ID + 1); + + if (lpc_did_hi_byte == 0x9D) + return PCH_LP; + else if (lpc_did_hi_byte == 0xA3) + return PCH_H; + else + return PCH_UNKNOWN_SERIES; +} + #if ENV_RAMSTAGE static void soc_mirror_dmi_pcr_io_dec(void) { |