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author | Subrata Banik <subrata.banik@intel.com> | 2018-06-21 11:52:21 +0530 |
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committer | Subrata Banik <subrata.banik@intel.com> | 2018-06-22 01:58:33 +0000 |
commit | d5018a8f78b9e1f0b7d3d1be298cba9716b10c6c (patch) | |
tree | 677c73abcfa2193e9c6aafc1144ae300e1fef864 /src/soc/intel/cannonlake/memmap.c | |
parent | f699c14c03a78549b0e5ed32cf9714473127c618 (diff) | |
download | coreboot-d5018a8f78b9e1f0b7d3d1be298cba9716b10c6c.tar.xz |
soc/intel/cannonlake: Remove DMA support for PTT
Alternative buffer communication support for PTT is no longer
needed for CNL onwards and coreboot does not need to reserve additional
4KiB memory for PTT support.
Change-Id: I11993cef77fd5e879eedabc1ed344f91f8257c90
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/27176
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/cannonlake/memmap.c')
-rw-r--r-- | src/soc/intel/cannonlake/memmap.c | 19 |
1 files changed, 0 insertions, 19 deletions
diff --git a/src/soc/intel/cannonlake/memmap.c b/src/soc/intel/cannonlake/memmap.c index 108a1b016c..64e07be38c 100644 --- a/src/soc/intel/cannonlake/memmap.c +++ b/src/soc/intel/cannonlake/memmap.c @@ -83,22 +83,6 @@ int smm_subregion(int sub, void **start, size_t *size) return 0; } -static bool is_ptt_enable(void) -{ - if ((read32((void *)PTT_TXT_BASE_ADDRESS) & PTT_PRESENT) == - PTT_PRESENT) - return true; - - return false; -} - -/* Calculate PTT size */ -static size_t get_ptt_size(void) -{ - /* Allocate 4KB for PTT if enabled */ - return is_ptt_enable() ? 4*KiB : 0; -} - /* Calculate ME Stolen size */ static size_t get_imr_size(void) { @@ -192,9 +176,6 @@ static size_t calculate_reserved_mem_size(uintptr_t dram_base, /* Get Tracehub size */ reserve_mem_base -= get_imr_size(); - /* Get PTT size */ - reserve_mem_base -= get_ptt_size(); - /* Traditional Area Size */ reserve_mem_size = dram_base - reserve_mem_base; |