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authorLijian Zhao <lijian.zhao@intel.com>2017-08-17 14:25:24 -0700
committerAaron Durbin <adurbin@chromium.org>2017-09-13 03:09:15 +0000
commit2b074d90ae0d20f2d3171f2ddc5d0b6c0d3b78b0 (patch)
tree1d06a3e7633e227a071e60bf6325ae345cc12e6c /src/soc/intel/cannonlake/pmutil.c
parent6732b4fcdcb48b21631ca73cd1ec37f497d21d3e (diff)
downloadcoreboot-2b074d90ae0d20f2d3171f2ddc5d0b6c0d3b78b0.tar.xz
soc/intel/cannonlake: Add common ACPI support for CNL
Basic ACPI support for CNL on top of common ACPI, which will establish a root of FADT table, fill MADT entry, create gnvs field, record wake status and convert device names into DSDT dev definitions. Change-Id: Ibc16d2afdd3cb9bad2ecb85cf320c88504409707 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21076 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/cannonlake/pmutil.c')
-rw-r--r--src/soc/intel/cannonlake/pmutil.c28
1 files changed, 0 insertions, 28 deletions
diff --git a/src/soc/intel/cannonlake/pmutil.c b/src/soc/intel/cannonlake/pmutil.c
index 322fe514e9..6708781fa5 100644
--- a/src/soc/intel/cannonlake/pmutil.c
+++ b/src/soc/intel/cannonlake/pmutil.c
@@ -125,34 +125,6 @@ const char *const *soc_gpe_sts_array(size_t *a)
return gpe_sts_bits;
}
-int acpi_sci_irq(void)
-{
- int scis = pci_read_config32(PCH_DEV_PMC, ACTL) & SCI_IRQ_SEL;
- int sci_irq = 9;
-
- /* Determine how SCI is routed. */
- switch (scis) {
- case SCIS_IRQ9:
- case SCIS_IRQ10:
- case SCIS_IRQ11:
- sci_irq = scis - SCIS_IRQ9 + 9;
- break;
- case SCIS_IRQ20:
- case SCIS_IRQ21:
- case SCIS_IRQ22:
- case SCIS_IRQ23:
- sci_irq = scis - SCIS_IRQ20 + 20;
- break;
- default:
- printk(BIOS_DEBUG, "Invalid SCI route! Defaulting to IRQ9.\n");
- sci_irq = 9;
- break;
- }
-
- printk(BIOS_DEBUG, "SCI is IRQ%d\n", sci_irq);
- return sci_irq;
-}
-
uint8_t *pmc_mmio_regs(void)
{
uint32_t reg32;