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authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-07-03 07:25:59 +0300
committerNico Huber <nico.h@gmx.de>2019-07-04 09:48:22 +0000
commit903b40a8a46b6e8d853f509480661c8174311f17 (patch)
treefd07ccd13dd831f2a30fac410c89125ed9eae1ce /src/soc/intel/cannonlake/pmutil.c
parent9c0e14e7c43e85e99c0bbfdff72019d908de1711 (diff)
downloadcoreboot-903b40a8a46b6e8d853f509480661c8174311f17.tar.xz
soc/intel: Replace uses of dev_find_slot()
To call dev_find_slot(0, xx) in romstage can produce invalid results since PCI bus enumeration has not been progressed yet. Replace this with method that relies on bus topology that walks the root bus only. Change-Id: I2883610059bb9fa860bba01179e7d5c58cae00e5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33996 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/soc/intel/cannonlake/pmutil.c')
-rw-r--r--src/soc/intel/cannonlake/pmutil.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/cannonlake/pmutil.c b/src/soc/intel/cannonlake/pmutil.c
index ab36c70c10..9997d164e4 100644
--- a/src/soc/intel/cannonlake/pmutil.c
+++ b/src/soc/intel/cannonlake/pmutil.c
@@ -177,7 +177,7 @@ void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2)
DEVTREE_CONST struct soc_intel_cannonlake_config *config;
/* Look up the device in devicetree */
- DEVTREE_CONST struct device *dev = dev_find_slot(0, PCH_DEVFN_PMC);
+ DEVTREE_CONST struct device *dev = pcidev_path_on_root(PCH_DEVFN_PMC);
if (!dev || !dev->chip_info) {
printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n");
return;