soc/intel/cannonlake: Fix chipset_power_state structure

This structure is declared as a static CAR_GLOBAL in the common
PMC library code and in the SOC specific code.  Remove the SOC
specific version and instead get the chipset_power_state pointer
from the PMC library.

This fixes events that were recorded in chipset_power_state at
boot but were reading as all zero when it was time to parse the
structure when logging events to flash.

Change-Id: I67a4f724c0707d98766ad28abd8d0b66a5615745
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/30717
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>

1 files changed, 1 insertions, 3 deletions

diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c
index 246e0eac05..9224ba6dea 100644
--- a/src/soc/intel/cannonlake/romstage/romstage.c
+++ b/src/soc/intel/cannonlake/romstage/romstage.c
@@ -33,8 +33,6 @@
 #include <string.h>
 #include <timestamp.h>
 
-static struct chipset_power_state power_state CAR_GLOBAL;
-
 #define FSP_SMBIOS_MEMORY_INFO_GUID	\
 {	\
 	0xd4, 0x71, 0x20, 0x9b, 0x54, 0xb0, 0x0c, 0x4e,	\
@@ -112,7 +110,7 @@ asmlinkage void car_stage_entry(void)
 	bool s3wake;
 	struct postcar_frame pcf;
 	uintptr_t top_of_ram;
-	struct chipset_power_state *ps = car_get_var_ptr(&power_state);
+	struct chipset_power_state *ps = pmc_get_power_state();
 
 	console_init();