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| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-06-18 13:19:29 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-06-21 08:59:15 +0000 |
| commit | 4821a0e135ff2d60f552203d2724ae2d44850623 (patch) | |
| tree | fbf6a703341fe1719b0d72f53d6da8f0d05ce5e2 /src/soc/intel/cannonlake/romstage | |
| parent | a6a396ddb6f866c5a675dff5c1aa0b4cbaf44039 (diff) | |
| download | coreboot-4821a0e135ff2d60f552203d2724ae2d44850623.tar.xz | |
soc/intel/cannonlake: Rename SOC_INTEL_COMMON_CANNONLAKE_BASE
What it really means to do is to use different FSP headers.
Change-Id: I3c75d4aac8525ab2639608fb9c1b3a9afef0e943
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33575
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/soc/intel/cannonlake/romstage')
| -rw-r--r-- | src/soc/intel/cannonlake/romstage/fsp_params.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index 77bad8f627..a1e3d76b4a 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -69,7 +69,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config) /* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */ m_cfg->VmxEnable = CONFIG(ENABLE_VMX); -#if CONFIG(SOC_INTEL_COMMON_CANNONLAKE_BASE) +#if CONFIG(SOC_INTEL_CANNONLAKE_ALTERNATE_HEADERS) m_cfg->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT; #endif |