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author | Pratik Prajapati <pratikkumar.v.prajapati@intel.com> | 2017-08-14 12:18:38 -0700 |
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committer | Aaron Durbin <adurbin@chromium.org> | 2017-08-21 19:46:43 +0000 |
commit | 7a357eb8657fd891aad33fd710d2f9d4d80c9130 (patch) | |
tree | 0b340a5a9c948512dace2f2ff963161629b18e83 /src/soc/intel/cannonlake/romstage | |
parent | 53d68b4ffb9f99f51a3634c263b8a9176d7ea1a6 (diff) | |
download | coreboot-7a357eb8657fd891aad33fd710d2f9d4d80c9130.tar.xz |
soc/intel/skylake: Fix SGX init sequence
Configure core PRMRR first on all the cores and then follow
the SGX init sequence. Second microcode load would run the
MCHECK. To pass MCHECK, PRMRR on all cores needs to be
configured first. Hence, PRMRR configuration would be called
from soc_core_init while MP init for each core and then from
soc_init_cpus, BSP would call sgx_configure for each core
(including for itself). This code flow satisfies the MCHECK
passing pre-conditions; and apparently this patch fixes the
behavior of calling configure_sgx() “again” for BSP. (So
removed the TODO comment also).
Change-Id: I88f330eb9757cdc3dbfc7609729c6ceb7d58a0e1
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21007
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/cannonlake/romstage')
0 files changed, 0 insertions, 0 deletions