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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-08-18 06:55:52 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-08-26 22:53:31 +0000 |
| commit | a7d2f2982364f7b9c0c0410f7ba07e6d6c7aa527 (patch) | |
| tree | 30a1b7d01f80c24b0504ab335dd0ab66895c0c0e /src/soc/intel/cannonlake/romstage | |
| parent | 8418fd418c8fcef5ca59109be33dececee9cda29 (diff) | |
| download | coreboot-a7d2f2982364f7b9c0c0410f7ba07e6d6c7aa527.tar.xz | |
intel/car: Use common TS_START_ROMSTAGE
This timestamp also got unintentionally removed from some
boards as they were transformed to use common romstage entry.
Change-Id: I12be278a674f9a2ea073b170a223c41c7fc01a94
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34970
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/cannonlake/romstage')
| -rw-r--r-- | src/soc/intel/cannonlake/romstage/romstage.c | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c index 5711c15142..fb5e42b200 100644 --- a/src/soc/intel/cannonlake/romstage/romstage.c +++ b/src/soc/intel/cannonlake/romstage/romstage.c @@ -28,7 +28,6 @@ #include <soc/pm.h> #include <soc/romstage.h> #include <string.h> -#include <timestamp.h> #include "../chip.h" @@ -137,7 +136,6 @@ void mainboard_romstage_entry(void) /* initialize Heci interface */ heci_init(HECI1_BASE_ADDRESS); - timestamp_add_now(TS_START_ROMSTAGE); s3wake = pmc_fill_power_state(ps) == ACPI_S3; fsp_memory_init(s3wake); pmc_set_disb(); |