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| author | Jamie Chen <jamie.chen@intel.com> | 2020-01-15 11:17:21 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-01-18 11:20:12 +0000 |
| commit | c004857da06dd90be9a1ac34bd6efe2bc03fed6a (patch) | |
| tree | 47f4043e511b22b72c1d3c7385ecb2c09f1f2737 /src/soc/intel/cannonlake/romstage | |
| parent | 1d8568c91413c76ee147bf6c09ae87197f7e75d7 (diff) | |
| download | coreboot-c004857da06dd90be9a1ac34bd6efe2bc03fed6a.tar.xz | |
soc/intel/cannonlake: Add chip config for SATA strength
Add config to chip.h for tuning SATA gen3 strength.
BUG=b:147351936
BRANCH=none
TEST=build successful in puff
Change-Id: I4dcd23834fa3c01c1d88697a7bb8cf361709b62e
Signed-off-by: Jamie Chen <jamie.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38432
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/cannonlake/romstage')
| -rw-r--r-- | src/soc/intel/cannonlake/romstage/fsp_params.c | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index 5c74d4a1e0..3c5be301b8 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -101,6 +101,28 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config) dev = pcidev_path_on_root(SA_DEVFN_IPU); if (dev) m_cfg->SaIpuEnable = dev->enabled; + + /* SATA Gen3 strength */ + for (i = 0; i < SOC_INTEL_CML_SATA_DEV_MAX; i++) { + if (config->sata_port[i].RxGen3EqBoostMagEnable) { + m_cfg->PchSataHsioRxGen3EqBoostMagEnable[i] = + config->sata_port[i].RxGen3EqBoostMagEnable; + m_cfg->PchSataHsioRxGen3EqBoostMag[i] = + config->sata_port[i].RxGen3EqBoostMag; + } + if (config->sata_port[i].TxGen3DownscaleAmpEnable) { + m_cfg->PchSataHsioTxGen3DownscaleAmpEnable[i] = + config->sata_port[i].TxGen3DownscaleAmpEnable; + m_cfg->PchSataHsioTxGen3DownscaleAmp[i] = + config->sata_port[i].TxGen3DownscaleAmp; + } + if (config->sata_port[i].TxGen3DeEmphEnable) { + m_cfg->PchSataHsioTxGen3DeEmphEnable[i] = + config->sata_port[i].TxGen3DeEmphEnable; + m_cfg->PchSataHsioTxGen3DeEmph[i] = + config->sata_port[i].TxGen3DeEmph; + } + } } void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) |