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| author | Subrata Banik <subrata.banik@intel.com> | 2017-11-23 13:58:34 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2017-12-02 03:20:15 +0000 |
| commit | 0baad61a4e2f66f91d18578a7260db19a3531caa (patch) | |
| tree | b636360c79b7a4795a422b857e8e2fc439ff82fd /src/soc/intel/cannonlake/systemagent.c | |
| parent | 2153ea5b83461547c854b2cd784b1638a3feeb31 (diff) | |
| download | coreboot-0baad61a4e2f66f91d18578a7260db19a3531caa.tar.xz | |
soc/intel/cannonlake: Initialize PMC controller
PMC controller gets hidden during FSP-Silicon initialization
using sideband interface on CannonLake platform. Hence accessing
PWRMBASE using PCI config space will return invalid BAR value as
0xFFFFF000. Also PMC PCI driver will not be able to initialize
PMC controller as its not showing over PCI bus.
coreboot PCI enumeration log shows:
PCI: Static device PCI: 00:1f.2 not found, disabling it.
This patch ensures PMC controller is getting initialized using
boot state machine right after FSP Silicon Init returns (BS_DEV_INIT_CHIPS/
BS_ON_EXIT).
TEST=Ensures PWRMBASE address is 0xFE000000 and PMC controller
is getting initialized during BS_DEV_INIT_CHIPES/BS_ON_EXIT.
Change-Id: Ife7389f0f035b66837aace89d6e6b866e494cbe4
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/cannonlake/systemagent.c')
| -rw-r--r-- | src/soc/intel/cannonlake/systemagent.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/systemagent.c b/src/soc/intel/cannonlake/systemagent.c index 7ce152dc21..344517d9e8 100644 --- a/src/soc/intel/cannonlake/systemagent.c +++ b/src/soc/intel/cannonlake/systemagent.c @@ -17,6 +17,7 @@ #include <console/console.h> #include <device/device.h> +#include <device/pci.h> #include <intelblocks/systemagent.h> #include <soc/iomap.h> #include <soc/systemagent.h> @@ -37,6 +38,17 @@ void soc_add_fixed_mmio_resources(struct device *dev, int *index) { EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" }, { REGBAR, REG_BASE_ADDRESS, REG_BASE_SIZE, "REGBAR" }, { EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" }, + /* + * PMC pci device gets hidden from PCI bus due to Silicon + * policy hence binding PMCBAR aka PWRMBASE (offset 0x10) with + * SA resources to ensure that PMCBAR falls under PCI reserved + * memory range. + * + * Note: Don't add any more resource with same offset 0x10 + * under this device space. + */ + { PCI_BASE_ADDRESS_0, PCH_PWRM_BASE_ADDRESS, PCH_PWRM_BASE_SIZE, + "PMCBAR" }, }; sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources, |