summaryrefslogtreecommitdiff
path: root/src/soc/intel/cannonlake/uart.c
diff options
context:
space:
mode:
authorPatrik Tesarik <mail@patrik-tesarik.de>2020-04-15 14:11:54 +0200
committerPatrick Georgi <pgeorgi@google.com>2020-05-04 09:52:34 +0000
commit066007590f5b904962f9965ace5485ddab7a89c3 (patch)
tree82b7f688a7470ad7f222dd957b2c869d16462018 /src/soc/intel/cannonlake/uart.c
parentf87ff33a898e93012112bf9a446182ac7e024bc8 (diff)
downloadcoreboot-066007590f5b904962f9965ace5485ddab7a89c3.tar.xz
mb/up/squared: Fix eMMC speed for UP2 with EDK2
Since commit 402fe20e (mb/up/squared: Add mainboard) the UP2's eMMC maximum host speed was reduced to DDR50, because HS200 showed I/O errors in the host kernel. We found out that with EDK2 master the correct Host Speed could not be set properly during EDK2 platform init. Therefore eMMC would not show up for boot device selection. This commit sets the eMMC MaxHostSpeed to the designed max value of the used eMMC on the UP2 board and furthermore drops the override from the ramstage.c. It's already set in the devicetree.cb. Though CRC errors are still visible in EDK II debug logs, no other negative effects have been observed. Signed-off-by: Patrik Tesarik <mail@patrik-tesarik.de> Change-Id: I8d53204d8a776efd560fbdea918f83e180813179 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40403 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/intel/cannonlake/uart.c')
0 files changed, 0 insertions, 0 deletions