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authorSubrata Banik <subrata.banik@intel.com>2019-07-08 14:49:22 +0530
committerSubrata Banik <subrata.banik@intel.com>2019-07-11 05:57:41 +0000
commit10a9432cc2ad77234442bd639194c5a80050854e (patch)
treece6f68feab9582d2ab62765cd0d9a3262bb62b69 /src/soc/intel/cannonlake
parent5b9948140f97eceb47ba026d7bad6dfa2a3c483d (diff)
downloadcoreboot-10a9432cc2ad77234442bd639194c5a80050854e.tar.xz
soc/intel/common/timer: Move USE_LEGACY_8254_TIMER into common/block/timer
This patch moves USE_LEGACY_8254_TIMER Kconfig into common/block/timer for better code sharing. Also ported CB:33512 for SPT and ICP PCH. Change-Id: Ic767ff97aaa3eb7fa35ffa38fa416d006eaa6e78 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34132 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/cannonlake')
-rw-r--r--src/soc/intel/cannonlake/Kconfig8
1 files changed, 0 insertions, 8 deletions
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index fed7f02dc6..4235b7a0ce 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -316,14 +316,6 @@ config SOC_INTEL_CANNONLAKE_DEBUG_CONSENT
Setting non-zero value will allow to use DBC or DCI to debug SOC.
PlatformDebugConsent in FspmUpd.h has the details.
-config USE_LEGACY_8254_TIMER
- bool "Use Legacy 8254 Timer"
- default y if PAYLOAD_SEABIOS
- default n
- help
- This sets the Enable8254ClockGating UPD, which according to the FSP Integration
- guide needs to be disabled in order to boot SeaBIOS, but should otherwise be enabled.
-
config PRERAM_CBMEM_CONSOLE_SIZE
hex
default 0xe00