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authorAamir Bohra <aamir.bohra@intel.com>2019-09-10 08:39:14 +0530
committerFurquan Shaikh <furquan@google.com>2019-09-12 06:19:53 +0000
commit87bb5f5e7a4476a2e9a70cc8d234fa0b479f1e26 (patch)
tree975b13fd344aa8af8f505fc6a7970e0c44a5b43f /src/soc/intel/cannonlake
parent0e3c245c6cf4b8fe415c3309098cd51795d90fcf (diff)
downloadcoreboot-87bb5f5e7a4476a2e9a70cc8d234fa0b479f1e26.tar.xz
soc/intel/cannonlake: Add config for sata devslp pad reset configuration
CML FSP now provides a provision to configure the SATA devslp GPIO pad reset configuration. This config would help set the the required pad reset configuration. BUG=b:133000685 Change-Id: I4eaea9c6da67f1274ad3e392046a68cddc1b99b6 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35306 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Diffstat (limited to 'src/soc/intel/cannonlake')
-rw-r--r--src/soc/intel/cannonlake/chip.h10
-rw-r--r--src/soc/intel/cannonlake/fsp_params.c5
2 files changed, 15 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index 2ebe017fbd..9c7c17147e 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -136,9 +136,19 @@ struct soc_intel_cannonlake_config {
Sata_AHCI,
Sata_RAID,
} SataMode;
+
+ /* SATA devslp pad reset configuration */
+ enum {
+ SataDevSlpResumeReset = 1,
+ SataDevSlpHostDeepReset = 3,
+ SataDevSlpPlatformReset = 5,
+ SataDevSlpDswReset = 7
+ } SataDevSlpRstConfig;
+
uint8_t SataSalpSupport;
uint8_t SataPortsEnable[8];
uint8_t SataPortsDevSlp[8];
+ uint8_t SataPortsDevSlpResetConfig[8];
/* Enable/Disable SLP_S0 with GBE Support. 0: disable, 1: enable */
uint8_t SlpS0WithGbeSupport;
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index 4038335787..f48a626be9 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -186,6 +186,11 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
sizeof(params->SataPortsEnable));
memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp,
sizeof(params->SataPortsDevSlp));
+#if CONFIG(SOC_INTEL_COMETLAKE)
+ memcpy(params->SataPortsDevSlpResetConfig,
+ config->SataPortsDevSlpResetConfig,
+ sizeof(params->SataPortsDevSlpResetConfig));
+#endif
}
/* Lan */