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authorElyes HAOUAS <ehaouas@noos.fr>2020-03-31 21:55:16 +0200
committerAngel Pons <th3fanbus@gmail.com>2020-04-09 14:51:41 +0000
commita895c32242836c4a6da6c3bbceefc102fdc77636 (patch)
tree7266a9cb708343d511675ae0a7bd62e824392452 /src/soc/intel/cannonlake
parentaf0f410c702bf3468ca9be0a4ea8e21c4f7a67d6 (diff)
downloadcoreboot-a895c32242836c4a6da6c3bbceefc102fdc77636.tar.xz
soc/intel: Remove unneeded whitespaces
Change-Id: Ib156ebede1ee24a1c7bd20d01792ec80cba8f37d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39991 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/intel/cannonlake')
-rw-r--r--src/soc/intel/cannonlake/acpi/lpit.asl2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/cannonlake/acpi/lpit.asl b/src/soc/intel/cannonlake/acpi/lpit.asl
index 6ae4975ee1..0d2d9c39f0 100644
--- a/src/soc/intel/cannonlake/acpi/lpit.asl
+++ b/src/soc/intel/cannonlake/acpi/lpit.asl
@@ -78,7 +78,7 @@ scope(\_SB)
/*
* Save the current PM bits then
* enable GPIO PM with MISCCFG_ENABLE_GPIO_PM_CONFIG
- */
+ */
If (CondRefOf (\_SB.PCI0.EGPM))
{
\_SB.PCI0.EGPM ()