soc/intel/cannonlake: Use common GPIO driver

Change-Id: I0bbdd641244f0c7baaa2146dcfde6431bde387c5
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/20074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

5 files changed, 626 insertions, 0 deletions

diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index 3012c6165b..b3f657e0bd 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -35,6 +35,7 @@ config CPU_SPECIFIC_OPTIONS
 	select SOC_INTEL_COMMON_BLOCK_SMBUS
 	select SOC_INTEL_COMMON_BLOCK_RTC
 	select SOC_INTEL_COMMON_BLOCK_CSE
+	select SOC_INTEL_COMMON_BLOCK_GPIO
 
 config UART_DEBUG
 	bool "Enable UART debug port."
diff --git a/src/soc/intel/cannonlake/gpio.c b/src/soc/intel/cannonlake/gpio.c
new file mode 100644
index 0000000000..2dd90f9f01
--- /dev/null
+++ b/src/soc/intel/cannonlake/gpio.c
@@ -0,0 +1,98 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 - 2017 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <intelblocks/gpio.h>
+#include <intelblocks/pcr.h>
+#include <soc/pcr_ids.h>
+
+static const struct reset_mapping rst_map[] = {
+	{ .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 0U << 30 },
+	{ .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 },
+	{ .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 },
+};
+
+static const struct reset_mapping rst_map_com0[] = {
+	{ .logical = PAD_CFG0_LOGICAL_RESET_PWROK, .chipset = 0U << 30 },
+	{ .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 },
+	{ .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 },
+	{ .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 3U << 30 },
+};
+
+static const struct pad_community cnl_communities[] = {
+	{ /* GPP A, B, G */
+		.port = PID_GPIOCOM0,
+		.first_pad = GPP_A0,
+		.last_pad = GPP_G7,
+		.num_gpi_regs = NUM_GPIO_COM0_GPI_REGS,
+		.pad_cfg_base = PAD_CFG_BASE,
+		.host_own_reg_0 = HOSTSW_OWN_REG_0,
+		.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
+		.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
+		.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
+		.name = "GPP_ABG",
+		.acpi_path = "\\_SB.PCI0.GPIO",
+		.reset_map = rst_map_com0,
+		.num_reset_vals = ARRAY_SIZE(rst_map_com0),
+	}, { /* GPP D, F, H */
+		.port = PID_GPIOCOM1,
+		.first_pad = GPP_D0,
+		.last_pad = GPP_H23,
+		.num_gpi_regs = NUM_GPIO_COM1_GPI_REGS,
+		.pad_cfg_base = PAD_CFG_BASE,
+		.host_own_reg_0 = HOSTSW_OWN_REG_0,
+		.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
+		.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
+		.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
+		.name = "GPP_DFH",
+		.acpi_path = "\\_SB.PCI0.GPIO",
+		.reset_map = rst_map,
+		.num_reset_vals = ARRAY_SIZE(rst_map),
+	}, { /* GPD */
+		.port = PID_GPIOCOM2,
+		.first_pad = GPD0,
+		.last_pad = GPD11,
+		.num_gpi_regs = NUM_GPIO_COM2_GPI_REGS,
+		.pad_cfg_base = PAD_CFG_BASE,
+		.host_own_reg_0 = HOSTSW_OWN_REG_0,
+		.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
+		.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
+		.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
+		.name = "GPD",
+		.acpi_path = "\\_SB.PCI0.GPIO",
+		.reset_map = rst_map,
+		.num_reset_vals = ARRAY_SIZE(rst_map),
+	}, { /* GPP C, E */
+		.port = PID_GPIOCOM3,
+		.first_pad = GPP_C0,
+		.last_pad = GPP_E23,
+		.num_gpi_regs = NUM_GPIO_COM3_GPI_REGS,
+		.pad_cfg_base = PAD_CFG_BASE,
+		.host_own_reg_0 = HOSTSW_OWN_REG_0,
+		.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
+		.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
+		.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
+		.name = "GPP_CE",
+		.acpi_path = "\\_SB.PCI0.GPIO",
+		.reset_map = rst_map,
+		.num_reset_vals = ARRAY_SIZE(rst_map),
+	}
+};
+
+const struct pad_community *soc_gpio_get_community(size_t *num_communities)
+{
+	*num_communities = ARRAY_SIZE(cnl_communities);
+	return cnl_communities;
+}
diff --git a/src/soc/intel/cannonlake/include/soc/gpio.h b/src/soc/intel/cannonlake/include/soc/gpio.h
new file mode 100644
index 0000000000..0d97f040fc
--- /dev/null
+++ b/src/soc/intel/cannonlake/include/soc/gpio.h
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_CANNONLAKE_GPIO_H_
+#define _SOC_CANNONLAKE_GPIO_H_
+
+#include <soc/gpio_defs.h>
+#include <intelblocks/gpio.h>
+
+#define CROS_GPIO_DEVICE_NAME	"INT344B:00"
+
+#endif
diff --git a/src/soc/intel/cannonlake/include/soc/gpio_defs.h b/src/soc/intel/cannonlake/include/soc/gpio_defs.h
new file mode 100644
index 0000000000..46ab1d98c6
--- /dev/null
+++ b/src/soc/intel/cannonlake/include/soc/gpio_defs.h
@@ -0,0 +1,251 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_CANNONLAKE_GPIO_DEFS_H_
+#define _SOC_CANNONLAKE_GPIO_DEFS_H_
+
+#ifndef __ACPI__
+#include <stddef.h>
+#endif
+#include <soc/gpio_soc_defs.h>
+
+
+#define GPIO_NUM_PAD_CFG_REGS   2 /* DW0, DW1 */
+
+#define NUM_GPIO_COMx_GPI_REGS(n)	\
+		(ALIGN_UP((n), GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP)
+
+#define NUM_GPIO_COM0_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM0_PADS)
+#define NUM_GPIO_COM1_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM1_PADS)
+#define NUM_GPIO_COM2_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM2_PADS)
+#define NUM_GPIO_COM3_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM3_PADS)
+
+#define NUM_GPI_STATUS_REGS	\
+		((NUM_GPIO_COM0_GPI_REGS) +\
+		(NUM_GPIO_COM1_GPI_REGS) +\
+		(NUM_GPIO_COM2_GPI_REGS) +\
+		(NUM_GPIO_COM3_GPI_REGS))
+/*
+ * IOxAPIC IRQs for the GPIOs
+ */
+
+/* Group A */
+#define GPP_A0_IRQ				0x18
+#define GPP_A1_IRQ				0x19
+#define GPP_A2_IRQ				0x1a
+#define GPP_A3_IRQ				0x1b
+#define GPP_A4_IRQ				0x1c
+#define GPP_A5_IRQ				0x1d
+#define GPP_A6_IRQ				0x1e
+#define GPP_A7_IRQ				0x1f
+#define GPP_A8_IRQ				0x20
+#define GPP_A9_IRQ				0x21
+#define GPP_A10_IRQ				0x22
+#define GPP_A11_IRQ				0x23
+#define GPP_A12_IRQ				0x24
+#define GPP_A13_IRQ				0x25
+#define GPP_A14_IRQ				0x26
+#define GPP_A15_IRQ				0x27
+#define GPP_A16_IRQ				0x28
+#define GPP_A17_IRQ				0x29
+#define GPP_A18_IRQ				0x2a
+#define GPP_A19_IRQ				0x2b
+#define GPP_A20_IRQ				0x2c
+#define GPP_A21_IRQ				0x2d
+#define GPP_A22_IRQ				0x2e
+#define GPP_A23_IRQ				0x2f
+/* Group B */
+#define GPP_B0_IRQ				0x30
+#define GPP_B1_IRQ				0x31
+#define GPP_B2_IRQ				0x32
+#define GPP_B3_IRQ				0x33
+#define GPP_B4_IRQ				0x34
+#define GPP_B5_IRQ				0x35
+#define GPP_B6_IRQ				0x36
+#define GPP_B7_IRQ				0x37
+#define GPP_B8_IRQ				0x38
+#define GPP_B9_IRQ				0x39
+#define GPP_B10_IRQ				0x3a
+#define GPP_B11_IRQ				0x3b
+#define GPP_B12_IRQ				0x3c
+#define GPP_B13_IRQ				0x3d
+#define GPP_B14_IRQ				0x3e
+#define GPP_B15_IRQ				0x3f
+#define GPP_B16_IRQ				0x40
+#define GPP_B17_IRQ				0x41
+#define GPP_B18_IRQ				0x42
+#define GPP_B19_IRQ				0x43
+#define GPP_B20_IRQ				0x44
+#define GPP_B21_IRQ				0x45
+#define GPP_B22_IRQ				0x46
+#define GPP_B23_IRQ				0x47
+/* Group C */
+#define GPP_C0_IRQ				0x48
+#define GPP_C1_IRQ				0x49
+#define GPP_C2_IRQ				0x4a
+#define GPP_C3_IRQ				0x4b
+#define GPP_C4_IRQ				0x4c
+#define GPP_C5_IRQ				0x4d
+#define GPP_C6_IRQ				0x4e
+#define GPP_C7_IRQ				0x4f
+#define GPP_C8_IRQ				0x50
+#define GPP_C9_IRQ				0x51
+#define GPP_C10_IRQ				0x52
+#define GPP_C11_IRQ				0x53
+#define GPP_C12_IRQ				0x54
+#define GPP_C13_IRQ				0x55
+#define GPP_C14_IRQ				0x56
+#define GPP_C15_IRQ				0x57
+#define GPP_C16_IRQ				0x58
+#define GPP_C17_IRQ				0x59
+#define GPP_C18_IRQ				0x5a
+#define GPP_C19_IRQ				0x5b
+#define GPP_C20_IRQ				0x5c
+#define GPP_C21_IRQ				0x5d
+#define GPP_C22_IRQ				0x5e
+#define GPP_C23_IRQ				0x5f
+/* Group D */
+#define GPP_D0_IRQ				0x60
+#define GPP_D1_IRQ				0x61
+#define GPP_D2_IRQ				0x62
+#define GPP_D3_IRQ				0x63
+#define GPP_D4_IRQ				0x64
+#define GPP_D5_IRQ				0x65
+#define GPP_D6_IRQ				0x66
+#define GPP_D7_IRQ				0x67
+#define GPP_D8_IRQ				0x68
+#define GPP_D9_IRQ				0x69
+#define GPP_D10_IRQ				0x6a
+#define GPP_D11_IRQ				0x6b
+#define GPP_D12_IRQ				0x6c
+#define GPP_D13_IRQ				0x6d
+#define GPP_D14_IRQ				0x6e
+#define GPP_D15_IRQ				0x6f
+#define GPP_D16_IRQ				0x70
+#define GPP_D17_IRQ				0x71
+#define GPP_D18_IRQ				0x72
+#define GPP_D19_IRQ				0x73
+#define GPP_D20_IRQ				0x74
+#define GPP_D21_IRQ				0x75
+#define GPP_D22_IRQ				0x76
+#define GPP_D23_IRQ				0x77
+/* Group E */
+#define GPP_E0_IRQ				0x18
+#define GPP_E1_IRQ				0x19
+#define GPP_E2_IRQ				0x1a
+#define GPP_E3_IRQ				0x1b
+#define GPP_E4_IRQ				0x1c
+#define GPP_E5_IRQ				0x1d
+#define GPP_E6_IRQ				0x1e
+#define GPP_E7_IRQ				0x1f
+#define GPP_E8_IRQ				0x20
+#define GPP_E9_IRQ				0x21
+#define GPP_E10_IRQ				0x22
+#define GPP_E11_IRQ				0x23
+#define GPP_E12_IRQ				0x24
+#define GPP_E13_IRQ				0x25
+#define GPP_E14_IRQ				0x26
+#define GPP_E15_IRQ				0x27
+#define GPP_E16_IRQ				0x28
+#define GPP_E17_IRQ				0x29
+#define GPP_E18_IRQ				0x2a
+#define GPP_E19_IRQ				0x2b
+#define GPP_E20_IRQ				0x2c
+#define GPP_E21_IRQ				0x2d
+#define GPP_E22_IRQ				0x2e
+#define GPP_E23_IRQ				0x2f
+/* Group F */
+#define GPP_F0_IRQ				0x30
+#define GPP_F1_IRQ				0x31
+#define GPP_F2_IRQ				0x32
+#define GPP_F3_IRQ				0x33
+#define GPP_F4_IRQ				0x34
+#define GPP_F5_IRQ				0x35
+#define GPP_F6_IRQ				0x36
+#define GPP_F7_IRQ				0x37
+#define GPP_F8_IRQ				0x38
+#define GPP_F9_IRQ				0x39
+#define GPP_F10_IRQ				0x3a
+#define GPP_F11_IRQ				0x3b
+#define GPP_F12_IRQ				0x3c
+#define GPP_F13_IRQ				0x3d
+#define GPP_F14_IRQ				0x3e
+#define GPP_F15_IRQ				0x3f
+#define GPP_F16_IRQ				0x40
+#define GPP_F17_IRQ				0x41
+#define GPP_F18_IRQ				0x42
+#define GPP_F19_IRQ				0x43
+#define GPP_F20_IRQ				0x44
+#define GPP_F21_IRQ				0x45
+#define GPP_F22_IRQ				0x46
+#define GPP_F23_IRQ				0x47
+/* Group G */
+#define GPP_G0_IRQ				0x6c
+#define GPP_G1_IRQ				0x6d
+#define GPP_G2_IRQ				0x6e
+#define GPP_G3_IRQ				0x6f
+#define GPP_G4_IRQ				0x70
+#define GPP_G5_IRQ				0x71
+#define GPP_G6_IRQ				0x72
+#define GPP_G7_IRQ				0x73
+/* Group GPD */
+#define GPD0_IRQ				0x60
+#define GPD1_IRQ				0x61
+#define GPD2_IRQ				0x62
+#define GPD3_IRQ				0x63
+#define GPD4_IRQ				0x64
+#define GPD5_IRQ				0x65
+#define GPD6_IRQ				0x66
+#define GPD7_IRQ				0x67
+#define GPD8_IRQ				0x68
+#define GPD9_IRQ				0x69
+#define GPD10_IRQ				0x6a
+#define GPD11_IRQ				0x6b
+/* Group H */
+#define GPP_H0_IRQ				0x48
+#define GPP_H1_IRQ				0x49
+#define GPP_H2_IRQ				0x4a
+#define GPP_H3_IRQ				0x4b
+#define GPP_H4_IRQ				0x4c
+#define GPP_H5_IRQ				0x4d
+#define GPP_H6_IRQ				0x4e
+#define GPP_H7_IRQ				0x4f
+#define GPP_H8_IRQ				0x50
+#define GPP_H9_IRQ				0x51
+#define GPP_H10_IRQ				0x52
+#define GPP_H11_IRQ				0x53
+#define GPP_H12_IRQ				0x54
+#define GPP_H13_IRQ				0x55
+#define GPP_H14_IRQ				0x56
+#define GPP_H15_IRQ				0x57
+#define GPP_H16_IRQ				0x58
+#define GPP_H17_IRQ				0x59
+#define GPP_H18_IRQ				0x5a
+#define GPP_H19_IRQ				0x5b
+#define GPP_H20_IRQ				0x5c
+#define GPP_H21_IRQ				0x5d
+#define GPP_H22_IRQ				0x5e
+#define GPP_H23_IRQ				0x5f
+
+/* Register defines. */
+#define GPIO_MISCCFG				0x10
+#define  GPE_DW_SHIFT				8
+#define  GPE_DW_MASK				0xfff00
+#define HOSTSW_OWN_REG_0			0xb0
+#define GPI_SMI_STS_0				0x180
+#define GPI_SMI_EN_0				0x1A0
+#define PAD_CFG_BASE				0x600
+
+#endif
diff --git a/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h b/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h
new file mode 100644
index 0000000000..cdc40d4216
--- /dev/null
+++ b/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h
@@ -0,0 +1,252 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ * Copyright 2017 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_CANNONLAKE_GPIO_SOC_DEFS_H_
+#define _SOC_CANNONLAKE_GPIO_SOC_DEFS_H_
+
+/*
+ * There are 9 GPIO groups. GPP_A -> GPP_H and GPD. GPD is the special case
+ * where that group is not so generic. So most of the fixed numbers and macros
+ * are based on the GPP groups. The GPIO groups are accessed through register
+ * blocks called communities.
+ */
+#define GPP_A			0
+#define GPP_B			1
+#define GPP_G			2
+#define GPP_D			3
+#define GPP_F			4
+#define GPP_H			5
+#define GPP_C			6
+#define GPP_E			7
+#define GPD			8
+#define GPIO_NUM_GROUPS		9
+#define GPIO_MAX_NUM_PER_GROUP	24
+
+/*
+ * GPIOs are ordered monotonically increasing to match ACPI/OS driver.
+ */
+
+/* Group A */
+#define GPP_A0			0
+#define GPP_A1			1
+#define GPP_A2			2
+#define GPP_A3			3
+#define GPP_A4			4
+#define GPP_A5			5
+#define GPP_A6			6
+#define GPP_A7			7
+#define GPP_A8			8
+#define GPP_A9			9
+#define GPP_A10			10
+#define GPP_A11			11
+#define GPP_A12			12
+#define GPP_A13			13
+#define GPP_A14			14
+#define GPP_A15			15
+#define GPP_A16			16
+#define GPP_A17			17
+#define GPP_A18			18
+#define GPP_A19			19
+#define GPP_A20			20
+#define GPP_A21			21
+#define GPP_A22			22
+#define GPP_A23			23
+/* Group B */
+#define GPP_B0			24
+#define GPP_B1			25
+#define GPP_B2			26
+#define GPP_B3			27
+#define GPP_B4			28
+#define GPP_B5			29
+#define GPP_B6			30
+#define GPP_B7			31
+#define GPP_B8			32
+#define GPP_B9			33
+#define GPP_B10			34
+#define GPP_B11			35
+#define GPP_B12			36
+#define GPP_B13			37
+#define GPP_B14			38
+#define GPP_B15			39
+#define GPP_B16			40
+#define GPP_B17			41
+#define GPP_B18			42
+#define GPP_B19			43
+#define GPP_B20			44
+#define GPP_B21			45
+#define GPP_B22			46
+#define GPP_B23			47
+/* Group G */
+#define GPP_G0			48
+#define GPP_G1			49
+#define GPP_G2			50
+#define GPP_G3			51
+#define GPP_G4			52
+#define GPP_G5			53
+#define GPP_G6			54
+#define GPP_G7			55
+
+#define NUM_GPIO_COM0_PADS	(GPP_G7 - GPP_A0 + 1)
+
+/* Group D */
+#define GPP_D0			56
+#define GPP_D1			57
+#define GPP_D2			58
+#define GPP_D3			59
+#define GPP_D4			60
+#define GPP_D5			61
+#define GPP_D6			62
+#define GPP_D7			63
+#define GPP_D8			64
+#define GPP_D9			65
+#define GPP_D10			66
+#define GPP_D11			67
+#define GPP_D12			68
+#define GPP_D13			69
+#define GPP_D14			70
+#define GPP_D15			71
+#define GPP_D16			72
+#define GPP_D17			73
+#define GPP_D18			74
+#define GPP_D19			75
+#define GPP_D20			76
+#define GPP_D21			77
+#define GPP_D22			78
+#define GPP_D23			79
+/* Group F */
+#define GPP_F0			80
+#define GPP_F1			81
+#define GPP_F2			82
+#define GPP_F3			83
+#define GPP_F4			84
+#define GPP_F5			85
+#define GPP_F6			86
+#define GPP_F7			87
+#define GPP_F8			88
+#define GPP_F9			89
+#define GPP_F10			90
+#define GPP_F11			91
+#define GPP_F12			92
+#define GPP_F13			93
+#define GPP_F14			94
+#define GPP_F15			95
+#define GPP_F16			96
+#define GPP_F17			97
+#define GPP_F18			98
+#define GPP_F19			99
+#define GPP_F20			100
+#define GPP_F21			101
+#define GPP_F22			102
+#define GPP_F23			103
+/* Group H */
+#define GPP_H0			104
+#define GPP_H1			105
+#define GPP_H2			106
+#define GPP_H3			107
+#define GPP_H4			108
+#define GPP_H5			109
+#define GPP_H6			110
+#define GPP_H7			111
+#define GPP_H8			112
+#define GPP_H9			113
+#define GPP_H10			114
+#define GPP_H11			115
+#define GPP_H12			116
+#define GPP_H13			117
+#define GPP_H14			118
+#define GPP_H15			119
+#define GPP_H16			120
+#define GPP_H17			121
+#define GPP_H18			122
+#define GPP_H19			123
+#define GPP_H20			124
+#define GPP_H21			125
+#define GPP_H22			126
+#define GPP_H23			127
+
+#define NUM_GPIO_COM1_PADS	(GPP_H23 - GPP_D0 + 1)
+
+/* Group C */
+#define GPP_C0			128
+#define GPP_C1			129
+#define GPP_C2			130
+#define GPP_C3			131
+#define GPP_C4			132
+#define GPP_C5			133
+#define GPP_C6			134
+#define GPP_C7			135
+#define GPP_C8			136
+#define GPP_C9			137
+#define GPP_C10			138
+#define GPP_C11			139
+#define GPP_C12			140
+#define GPP_C13			141
+#define GPP_C14			142
+#define GPP_C15			143
+#define GPP_C16			144
+#define GPP_C17			145
+#define GPP_C18			146
+#define GPP_C19			147
+#define GPP_C20			148
+#define GPP_C21			149
+#define GPP_C22			150
+#define GPP_C23			151
+/* Group E */
+#define GPP_E0			152
+#define GPP_E1			153
+#define GPP_E2			154
+#define GPP_E3			155
+#define GPP_E4			156
+#define GPP_E5			157
+#define GPP_E6			158
+#define GPP_E7			159
+#define GPP_E8			160
+#define GPP_E9			161
+#define GPP_E10			162
+#define GPP_E11			163
+#define GPP_E12			164
+#define GPP_E13			165
+#define GPP_E14			166
+#define GPP_E15			167
+#define GPP_E16			168
+#define GPP_E17			169
+#define GPP_E18			170
+#define GPP_E19			171
+#define GPP_E20			172
+#define GPP_E21			173
+#define GPP_E22			174
+#define GPP_E23			175
+
+#define NUM_GPIO_COM3_PADS	(GPP_E23 - GPP_C0 + 1)
+
+/* Group GPD  */
+#define GPD0			176
+#define GPD1			177
+#define GPD2			178
+#define GPD3			179
+#define GPD4			180
+#define GPD5			181
+#define GPD6			182
+#define GPD7			183
+#define GPD8			184
+#define GPD9			185
+#define GPD10			186
+#define GPD11			187
+
+#define NUM_GPIO_COM2_PADS	(GPD11 - GPD0 + 1)
+
+#endif
+