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| author | Lijian Zhao <lijian.zhao@intel.com> | 2018-12-06 15:05:19 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-12-19 05:30:23 +0000 |
| commit | ba8202948ab77bdbd3dc2197f1552b87791a659a (patch) | |
| tree | 0ccd235ac9809e6e50f043c7a659ba34e69fd69c /src/soc/intel/cannonlake | |
| parent | fd02ff0375d72b7e50d697446c877c3c8ad94efc (diff) | |
| download | coreboot-ba8202948ab77bdbd3dc2197f1552b87791a659a.tar.xz | |
soc/intel/cannonlake: Declare SATA Mode clear
FSP support two SATA modes as AHCI mode (0) and RAID mode (1), make it
more clear in header file.
Change-Id: I1edcadc0048df839da145260b60f9f7720d981fe
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/30093
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/cannonlake')
| -rw-r--r-- | src/soc/intel/cannonlake/chip.h | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 8eaf02b204..962748f561 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -124,7 +124,10 @@ struct soc_intel_cannonlake_config { uint16_t usb3_wake_enable_bitmap; /* SATA related */ - uint8_t SataMode; + enum { + Sata_AHCI, + Sata_RAID, + } SataMode; uint8_t SataSalpSupport; uint8_t SataPortsEnable[8]; uint8_t SataPortsDevSlp[8]; |