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| author | Michael Niewöhner <foss@mniewoehner.de> | 2020-09-04 15:40:35 +0200 |
|---|---|---|
| committer | Michael Niewöhner <c0d3z3r0@review.coreboot.org> | 2020-09-06 14:26:33 +0000 |
| commit | 056d5523578dea5968d14ad1277ea263a5be7796 (patch) | |
| tree | 80f3efd6e62e8d3926a897ff8b8a28f1f823ae0f /src/soc/intel/cannonlake | |
| parent | b3ced6a67b6f950d06bebf413d98218969b75b57 (diff) | |
| download | coreboot-056d5523578dea5968d14ad1277ea263a5be7796.tar.xz | |
soc/intel: skl,cnl,icl,jsl,tgl: disable usb over-current pin by default
Fsp configures the USB over-current pin and overrides the according pad
configuration to NF1, regardless of the port being configured as disabled.
Thus, set the OC pin to 0xff ("disabled") in this case to prevent this.
This allows us to skip setting USBx_PORT_EMPTY in the devicetree for
disabled USB ports.
Change-Id: Ib8ea2ea26c0623d4db910e487b37255e907b299d
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45112
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/cannonlake')
| -rw-r--r-- | src/soc/intel/cannonlake/fsp_params.c | 21 |
1 files changed, 10 insertions, 11 deletions
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 615a94f32e..63a85c2db0 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -262,15 +262,6 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) /* Load VBT before devicetree-specific config. */ params->GraphicsConfigPtr = (uintptr_t)vbt_get(); - /* Set USB OC pin to 0 first */ - for (i = 0; i < ARRAY_SIZE(params->Usb2OverCurrentPin); i++) { - params->Usb2OverCurrentPin[i] = 0; - } - - for (i = 0; i < ARRAY_SIZE(params->Usb3OverCurrentPin); i++) { - params->Usb3OverCurrentPin[i] = 0; - } - mainboard_silicon_init_params(params); const struct soc_power_limits_config *soc_config; @@ -379,12 +370,16 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) /* USB */ for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { params->PortUsb20Enable[i] = config->usb2_ports[i].enable; - params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin; params->Usb2AfePetxiset[i] = config->usb2_ports[i].pre_emp_bias; params->Usb2AfeTxiset[i] = config->usb2_ports[i].tx_bias; params->Usb2AfePredeemp[i] = config->usb2_ports[i].tx_emp_enable; params->Usb2AfePehalfbit[i] = config->usb2_ports[i].pre_emp_bit; + + if (config->usb2_ports[i].enable) + params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin; + else + params->Usb2OverCurrentPin[i] = 0xff; } if (config->PchUsb2PhySusPgDisable) @@ -392,7 +387,11 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { params->PortUsb30Enable[i] = config->usb3_ports[i].enable; - params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin; + if (config->usb3_ports[i].enable) { + params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin; + } else { + params->Usb3OverCurrentPin[i] = 0xff; + } if (config->usb3_ports[i].tx_de_emp) { params->Usb3HsioTxDeEmphEnable[i] = 1; params->Usb3HsioTxDeEmph[i] = |