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| author | Nico Huber <nico.h@gmx.de> | 2019-10-12 15:16:33 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-26 15:01:00 +0000 |
| commit | 9ea70c02cd0e5e28f38136ebbb6dbad72ad177c7 (patch) | |
| tree | 68af4367507ca483522d2013b64c3e2e83511b67 /src/soc/intel/cannonlake | |
| parent | 95dcf29b2fcc9f7c02812d760ec0be492d5b7580 (diff) | |
| download | coreboot-9ea70c02cd0e5e28f38136ebbb6dbad72ad177c7.tar.xz | |
intel/cannonlake: Implement PCIe RP devicetree update
Some existing devicetrees were manually adapted to anticipate
root-port switching. Now, their PCI-device on/off settings should
just reflect the `PcieRpEnable` state and configuration happens
on the PCI function that was assigned at reset.
Change-Id: I4d76f38c222b74053c6a2f80b492d4660ab4db6d
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/intel/cannonlake')
| -rw-r--r-- | src/soc/intel/cannonlake/chip.c | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c index 51678add67..ef85215623 100644 --- a/src/soc/intel/cannonlake/chip.c +++ b/src/soc/intel/cannonlake/chip.c @@ -7,6 +7,7 @@ #include <intelblocks/acpi.h> #include <intelblocks/cfg.h> #include <intelblocks/itss.h> +#include <intelblocks/pcie_rp.h> #include <intelblocks/xdci.h> #include <romstage_handoff.h> #include <soc/intel/common/vbt.h> @@ -16,6 +17,19 @@ #include "chip.h" +static const struct pcie_rp_group pch_lp_rp_groups[] = { + { .slot = PCH_DEV_SLOT_PCIE, .count = 8 }, + { .slot = PCH_DEV_SLOT_PCIE_1, .count = 8 }, + { 0 } +}; + +static const struct pcie_rp_group pch_h_rp_groups[] = { + { .slot = PCH_DEV_SLOT_PCIE, .count = 8 }, + { .slot = PCH_DEV_SLOT_PCIE_1, .count = 8 }, + { .slot = PCH_DEV_SLOT_PCIE_2, .count = 8 }, + { 0 } +}; + #if CONFIG(HAVE_ACPI_TABLES) const char *soc_acpi_name(const struct device *dev) { @@ -166,6 +180,12 @@ void soc_init_pre_device(void *chip_info) cnl_configure_pads(NULL, 0); soc_gpio_pm_configuration(); + + /* swap enabled PCI ports in device tree if needed */ + if (CONFIG(SOC_INTEL_CANNONLAKE_PCH_H)) + pcie_rp_update_devicetree(pch_h_rp_groups); + else + pcie_rp_update_devicetree(pch_lp_rp_groups); } static struct device_operations pci_domain_ops = { |