diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2017-09-15 15:23:04 -0600 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-09-20 23:54:42 +0000 |
| commit | 0990fbf2d9b8a0070866788b185bdd4bf6e5537e (patch) | |
| tree | 85b2b519e9d0d5451fc1c63c93bcbdc4552e0cd2 /src/soc/intel/cannonlake | |
| parent | fe265a1b9ce7ad5b3dbd19f5857a902494bbe24e (diff) | |
| download | coreboot-0990fbf2d9b8a0070866788b185bdd4bf6e5537e.tar.xz | |
vboot: reset vbnv in cmos when cmos failure occurs
There's an occasional issue on machines which use CMOS for their
vbnv storage. The machine that just powers up from complete G3
would have had their RTC rail not held up. The contents of vbnv
in CMOS could pass the crc8 though the values could be bad. In
order to fix this introduce two functions:
1. vbnv_init_cmos()
2. vbnv_cmos_failed()
At the start of vboot the CMOS is queried for failure. If there
is a failure indicated then the vbnv data is restored from flash
backup or reset to known values when there is no flash backup.
BUG=b:63054105
Change-Id: I8bd6f28f64a116b84a08ce4779cd4dc73c0f2f3d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/cannonlake')
| -rw-r--r-- | src/soc/intel/cannonlake/pmutil.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/pmutil.c b/src/soc/intel/cannonlake/pmutil.c index ebd3d61cc8..cee3f95a10 100644 --- a/src/soc/intel/cannonlake/pmutil.c +++ b/src/soc/intel/cannonlake/pmutil.c @@ -40,6 +40,7 @@ #include <soc/pm.h> #include <soc/smbus.h> #include <timer.h> +#include <vboot/vbnv.h> #include "chip.h" /* @@ -207,3 +208,8 @@ int soc_get_rtc_failed(void) return rtc_failed(ps->gen_pmcon_b); } + +int vbnv_cmos_failed(void) +{ + return rtc_failed(read32(pmc_mmio_regs() + GEN_PMCON_B)); +} |