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| author | V Sowmya <v.sowmya@intel.com> | 2019-01-07 13:11:29 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-01-09 09:52:44 +0000 |
| commit | 0bc3e3d590f591febd9ee6b1fbfa762c1dfea325 (patch) | |
| tree | c9e9e89f84cf0f00af962dbb31969a654f81dd74 /src/soc/intel/cannonlake | |
| parent | 26a52f492b87196f3823a9cca0abe6292354a837 (diff) | |
| download | coreboot-0bc3e3d590f591febd9ee6b1fbfa762c1dfea325.tar.xz | |
soc/intel/cannonlake: Enable/Disable IPU based on devicetree switch
This patch provides an option to enable or disable IPU (image processing unit),
* Add an entry for SA IPU in the pci_devs.h.
* Enable/Disable the IPU based on devicetree entry.
Change-Id: Ia155bc242dd33e816d056bbea1e3d4c1cbbe23da
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/30698
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel/cannonlake')
| -rw-r--r-- | src/soc/intel/cannonlake/include/soc/pci_devs.h | 4 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/romstage/fsp_params.c | 5 |
2 files changed, 9 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/include/soc/pci_devs.h b/src/soc/intel/cannonlake/include/soc/pci_devs.h index 77ae746bd8..005cda3bc3 100644 --- a/src/soc/intel/cannonlake/include/soc/pci_devs.h +++ b/src/soc/intel/cannonlake/include/soc/pci_devs.h @@ -47,6 +47,10 @@ #define SA_DEVFN_DSP _SA_DEVFN(DSP) #define SA_DEV_DSP _SA_DEV(DSP) +#define SA_DEV_SLOT_IPU 0x05 +#define SA_DEVFN_IPU _SA_DEVFN(IPU) +#define SA_DEV_IPU _SA_DEV(IPU) + /* PCH Devices */ #define PCH_DEV_SLOT_THERMAL 0x12 #define PCH_DEVFN_THERMAL _PCH_DEVFN(THERMAL, 0) diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index c3a2509063..91810e8e6e 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -67,6 +67,11 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config) else m_cfg->PchHdaEnable = dev->enabled; + /* Enable IPU only if the device is enabled */ + m_cfg->SaIpuEnable = 0; + dev = pcidev_path_on_root(SA_DEVFN_IPU); + if (dev) + m_cfg->SaIpuEnable = dev->enabled; } void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) |