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| author | Ronak Kanabar <ronak.kanabar@intel.com> | 2019-02-12 22:52:01 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-02-13 13:04:38 +0000 |
| commit | 3bb8c244f25e0f390f463a42ac0ec65a3a595e30 (patch) | |
| tree | 2a26cd0cb8ffd0e8c1c64297123dfe7a98e50886 /src/soc/intel/cannonlake | |
| parent | f1690f0ec166c214a2c42acf2d410ea7f35a77f0 (diff) | |
| download | coreboot-3bb8c244f25e0f390f463a42ac0ec65a3a595e30.tar.xz | |
soc/intel/cannonlake: Configure serial debug uart
Set SerialIoDebugUartNumber to CONFIG_UART_FOR_CONSOLE
SerialIoDebugUartNumber UPD use to select UART Number for Debug Purpose
The default value of SerialIoDebugUartNumber is 2 by default it selects UART 2
so it needs to be initialized as per board config
BUG=b:123702398
Change-Id: I91df4bb756e8ea86db112f1cc28687f48b2c0525
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/31375
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/cannonlake')
| -rw-r--r-- | src/soc/intel/cannonlake/fsp_params.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 866d9c8e92..c276c862e8 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -163,6 +163,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) dev->enabled = 0; params->XdciEnable = dev->enabled; + /* Set Debug serial port */ + params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE; + /* Enable CNVi Wifi if enabled in device tree */ dev = dev_find_slot(0, PCH_DEVFN_CNViWIFI); params->PchCnviMode = dev->enabled; |