soc/intel/cannonlake: Update PCIE CLKREQ programing

UPD of PCI express clock request was updated in FSP 7.0.14.11,
change that in coreboot accordingly.

TEST=NONE

Change-Id: I2261deccfb489c0de577d580997744a484f07a04
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21878
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

4 files changed, 36 insertions, 4 deletions

diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c
index 39e8e8ba33..23e6fffbe8 100644
--- a/src/soc/intel/cannonlake/chip.c
+++ b/src/soc/intel/cannonlake/chip.c
@@ -66,6 +66,10 @@ static const char *soc_acpi_name(const struct device *dev)
 	case PCH_DEVFN_PCIE10:	return "RP10";
 	case PCH_DEVFN_PCIE11:	return "RP11";
 	case PCH_DEVFN_PCIE12:	return "RP12";
+	case PCH_DEVFN_PCIE13:	return "RP13";
+	case PCH_DEVFN_PCIE14:	return "RP14";
+	case PCH_DEVFN_PCIE15:	return "RP15";
+	case PCH_DEVFN_PCIE16:	return "RP16";
 	case PCH_DEVFN_UART0:	return "UAR0";
 	case PCH_DEVFN_UART1:	return "UAR1";
 	case PCH_DEVFN_GSPI0:	return "SPI0";
@@ -173,7 +177,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 	int i;
 	FSP_S_CONFIG *params = &supd->FspsConfig;
 	const struct device *dev = SA_DEV_ROOT;
-	const config_t *config = dev->chip_info;
+	config_t *config = dev->chip_info;
 
 	/* Parse device tree and enable/disable devices */
 	parse_devicetree(params);
@@ -241,6 +245,16 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 
 	params->XdciEnable = config->XdciEnable;
 
+	/* PCI Express */
+	for (i = 0; i < ARRAY_SIZE(config->PcieClkSrcUsage); i++) {
+		if (config->PcieClkSrcUsage[i] == 0)
+			config->PcieClkSrcUsage[i] = PCIE_CLK_NOTUSED;
+	}
+	memcpy(params->PcieClkSrcUsage, config->PcieClkSrcUsage,
+	       sizeof(config->PcieClkSrcUsage));
+	memcpy(params->PcieClkSrcClkReq, config->PcieClkSrcClkReq,
+	       sizeof(config->PcieClkSrcClkReq));
+
 	/* eMMC and SD */
 	params->ScsEmmcEnabled = config->ScsEmmcEnabled;
 	params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled;
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index ee908f0a4c..0cfa3c3eab 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -20,6 +20,7 @@
 
 #include <intelblocks/gspi.h>
 #include <stdint.h>
+#include <soc/pch.h>
 #include <soc/serialio.h>
 #include <soc/usb.h>
 #include <soc/vr_config.h>
@@ -131,10 +132,15 @@ struct soc_intel_cannonlake_config {
 	/* Enable/Disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1 */
 	uint8_t PchHdaAudioLinkHda;
 
-	/* Pcie Root Ports */
+	/* PCIe Root Ports */
 	uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS];
-	uint8_t PcieRpClkReqSupport[CONFIG_MAX_ROOT_PORTS];
-	uint8_t PcieRpClkReqNumber[CONFIG_MAX_ROOT_PORTS];
+	/* PCIe ouput clocks type to Pcie devices.
+	 * 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use,
+	 * 0xFF: not used */
+	uint8_t PcieClkSrcUsage[CONFIG_MAX_ROOT_PORTS];
+	/* PCIe ClkReq-to-ClkSrc mapping, number of clkreq signal assigned to
+	 * clksrc. */
+	uint8_t PcieClkSrcClkReq[CONFIG_MAX_ROOT_PORTS];
 
 	/* SMBus */
 	uint8_t SmbusEnable;
diff --git a/src/soc/intel/cannonlake/include/soc/pch.h b/src/soc/intel/cannonlake/include/soc/pch.h
index d8b3b955b6..7c21dd4b22 100644
--- a/src/soc/intel/cannonlake/include/soc/pch.h
+++ b/src/soc/intel/cannonlake/include/soc/pch.h
@@ -24,6 +24,10 @@
 #define PCH_LP				2
 #define PCH_UNKNOWN_SERIES		0xFF
 
+#define PCIE_CLK_NOTUSED		0xFF
+#define PCIE_CLK_LAN			0x70
+#define PCIE_CLK_FREE			0x80
+
 u8 pch_revision(void);
 u16 pch_type(void);
 void pch_log_state(void);
diff --git a/src/soc/intel/cannonlake/include/soc/pci_devs.h b/src/soc/intel/cannonlake/include/soc/pci_devs.h
index ed6b67030b..285fbd68e5 100644
--- a/src/soc/intel/cannonlake/include/soc/pci_devs.h
+++ b/src/soc/intel/cannonlake/include/soc/pci_devs.h
@@ -134,10 +134,18 @@
 #define  PCH_DEVFN_PCIE10	_PCH_DEVFN(PCIE_1, 1)
 #define  PCH_DEVFN_PCIE11	_PCH_DEVFN(PCIE_1, 2)
 #define  PCH_DEVFN_PCIE12	_PCH_DEVFN(PCIE_1, 3)
+#define  PCH_DEVFN_PCIE13	_PCH_DEVFN(PCIE_1, 4)
+#define  PCH_DEVFN_PCIE14	_PCH_DEVFN(PCIE_1, 5)
+#define  PCH_DEVFN_PCIE15	_PCH_DEVFN(PCIE_1, 6)
+#define  PCH_DEVFN_PCIE16	_PCH_DEVFN(PCIE_1, 7)
 #define  PCH_DEV_PCIE9		_PCH_DEV(PCIE_1, 0)
 #define  PCH_DEV_PCIE10		_PCH_DEV(PCIE_1, 1)
 #define  PCH_DEV_PCIE11		_PCH_DEV(PCIE_1, 2)
 #define  PCH_DEV_PCIE12		_PCH_DEV(PCIE_1, 3)
+#define  PCH_DEV_PCIE13		_PCH_DEV(PCIE_1, 4)
+#define  PCH_DEV_PCIE14		_PCH_DEV(PCIE_1, 5)
+#define  PCH_DEV_PCIE15		_PCH_DEV(PCIE_1, 6)
+#define  PCH_DEV_PCIE16		_PCH_DEV(PCIE_1, 7)
 
 #define PCH_DEV_SLOT_SIO3	0x1e
 #define  PCH_DEVFN_UART0	_PCH_DEVFN(SIO3, 0)